Slide 2 of 16
Notes:
Five of the key attributes that can be used to identify the best solution for the C54x vs. the C6x are: performance, power, price, packaging, and primary coding methodology. The performance ratio of C6x vs. C54x is 5-to-1. While there is a 10x improvement of the C6x versus typical 16-bit architectures in use today (C5x, 16xx from Lucent, etc.), there is a 5-times improvement of C6x over C54x. The power dissipation of the C6x is estimated to be about 3W. The C54x power dissipation for 100 MIPS device is projected at 115 mW. How is 115 mW determined? If you consider the 100 MIPS LC549 (which uses a 2.5V core, 3.3V I/O), the calculation would be: (2.5V)(.45 mA/MIPS)(100 MIPS) = 112.5 mW. If you consider a 66 MIPS LC548 with a 3.0V core, the calculation would be (3.0)(.6 mA/MIPS)(66 MIPS) = 118 mW. The C54x is optimized for lower power dissipation. The price of 25Ku LC548 or LC549 is around $33, while the C6x is about $97, which represents roughly a 3-to-1 ratio. The BGA (ball grid array) package of the C6x is 352 pins and is 35mm x 35mm, while the LC549 will be offered in a 144-pin BGA (called microStar BGA) that is 12mm x 12mm. The primary coding methodology for the C54x is assembly since it has a very efficient architecture for dense code size. The primary coding methodology for the C6x is “C” since the C6x is a highly efficient “C” engine.
