C54x Optimized Core

TO BUSES

MAC

ALU

17 X 17 MPY

40 BIT ADDER

RND, SAT

40 BIT ALU

CMPS OPERATOR (VITERBI)

EXP ENCODER

SHIFTER

ACCUMULATORS

40 BIT BARREL

(- 16, 31)

40 BIT ACC A

40 BIT ACC B

ADDRESSING UNIT

8 AUXILIARY REGISTERS

2 ADDRESSING UNITS

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The optimized CPU core has several components. The first and probably most important, is the multiply / accumulator or MAC. This particular device of the C54x family has a 17 X 17 multiplier rather than a 16 X 16 which is used on some other DSP product families. This enables unsigned by unsigned multiplication, signed by signed multiplication, and mixed-mode multiplication. It contains a 40-bit adder with 32-bit results and 8 bits of guard band and rounding & saturation control.

In addition, we see a 40-bit ALU which is capable of doing two 16-bit ALU operations. There's also a compare select store unit, the CMPS operator. This portion of the core allows you to accelerate Viterbi operations. There's an exponent encoder and two 40-bit accumulators. This differs from previous TI DSP families in that in the past we've had a single accumulator and in some cases an accumulator buffer.

Finally, we see a 40-bit barrel shifter and an addressing unit which houses eight auxiliary registers with two address generation units.