TMS320C80 Features

Key features of the TMS320C80:

• Up to 2 billion operations per second (BOPS)
• Four parallel processing advanced DSPs (PPs) with 64-bit instructions and 32-bit fixed-point data
  • Each PP is capable of many parallel operations per cycle
  • The PPs perform pixel/field processing as well as digital signal processing
• RISC master processor with 100-MFLOPS IEEE-754 floating-point unit
• 50K bytes of on-chip RAM
  • Supports many parallel accesses per cycle
• Crossbar switch supports up to 4.2G bytes/s transfer rates
  • 2.4G bytes/s of data and 1.8G bytes/s of instructions
  • 32K bytes of RAM can be shared by all processors and the transfer controller
• Transfer controller supports multidimensional packet transfers
  • 400M bytes/s on- and off-chip memory transfers
  • 4G-byte memory address space
  • Access to 8-, 16-, 32-, or 64-bit SRAM, VRAM, DRAM, SDRAM
  • Off-loads memory manipulations from the processors
• Video controller supports any display or capture resolution
• 0.5-mm CMOS technology
• Efficient packaging: 305-pin ceramic PGA

TMS320C80 Video Controller (VC)

The video controller is included only in the architecture of the 'C80 and is the interface between the device and image capture and display systems.

The 'C80 has two sets of frame timing counters and registers. The video controller keeps track of horizontal and vertical synchronization and blanking timing, as well as supporting a two-dimensional border region. Each counter has its own asynchronous clock inputs. These synchronization signals can individually be set up as outputs (for display) or inputs (for capture).

The shift register transfer (SRT) controller has comparators that cause shift register transfer cycles for VRAMs or cause packets transfers for DRAM-based display memories.

There are four main sections that make up the video controller:

• Frame timers
• Serial register transfer controller
• Register interface
• Multiplexer

Features of the video controller include:

• Two identical frame timers
  • They can be used for display or capture
  • Each has an asynchronous clock
  • They generate fully-programmable horizontal, vertical, blank, and border timing
• SRT controller
  • Controls two display/capture regions
  • VRAM shift register transfer control
  • Generates timer interrupts to the MP
  • Generates timer packet requests to the TC