Executive Summary
Device Features
'C67x Architecture
Device Specifications
Development Tools
Technical Documentation
TMS320C67x Third Parties
TMS320C67x Training
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TMS320C67x Assembly Benchmarks
TMS320C6000 Home

Key Features:

• 1 GFLOPS at 167 MHz
• VelociTI™ advanced VLIW architecture
• Industry's most advanced DSP C compiler
• Assembly Optimizer efficiently schedules tasks for maximum performance and ease in assembly language program
• Eight independent fuctional units
• Allows up to eight 32-bit instructions to be executed each cycle.

TI has added floating point capability to six of the eight functional units available on the C6x VelociTI™ architecture. Therefore, the ‘C67x instruction set is a superset of the ‘C62x fixed point instruction set. All ‘C62x instructions will run unmodified on the ‘C67x CPU. Following is a list of the 4 different functional units and their fixed and floating point capabilities.

L Unit:	32/40-bit fixed point arithmetic and compare operations 32/64-bit floating point arithmetic and compare operations (IEEE single and double precision) 32-bit fixed point logical operations fixed/floating point conversions 64 to 32-bit floating point conversions
S Unit:	32-bit fixed point arithmetic operations 32/40-bit shifts and 32-bit bit-field operations branching and constant generation 32/64-bit floating point reciprocal, absolute value, compares, and 1/sqrt operations 32 to 64-bit floating point conversions
M Unit:	16 x 16-bit fixed point multiplies 24 x 24-bit fixed point multiplies 32 x 32-bit fixed point multiplies 32 x 32-bit single precision floating point multiplies 64 x 64-bit double precision floating point multiplies
D Unit:	32-bit add, subtract, linear, and circular address calculation 8/16/32/64-bit loads 8/16/32-bit stores

These highly orthogonal functional units provide code generation tools with many execution resources enabling these tools to maximize performance without extensive hand-coding of assembly instructions by software developers. The ‘C67x’s instruction packing feature also allows these instructions to be executed in parallel, in serial or in parallel/serial combinations. This optimized scheme enables significant reductions in code size, program fetches and power consumption.

Just like with the ‘C62x, the ‘C67x core includes 8-, 16- and 32-byte addressability; 8 bits of overflow protection; saturation; bit-field extract, set and clear; bit counting; normalization and two additional integer multiply functional units with 32-bit and 24-bit multiply support.

TMS320C67x CPU Core

• 1 GFLOPS, 167 MHz
  • 6-ns cycle time
  • 6, 32-bit floating-point instructions per cycle
• Load store architecture
• Dual data paths
  • 8, 32-bit instructions/cycle
• IEEE Floating-Point Format
  • 1 GFLOPS Single-Precision
  • 420 MFLOPS Double-Precision - Hardware Supported

• CPU -
  Dual Data Path
  8 Functional Units
• Additional Integer Multiply Instructions not available on the C62x core
  • 32-bit multiply
  • 24-bit multiply
• Integer Instruction Features
  • Data Byte Addressable (8-, 16-, 32-bit data)
  • 8-bits Overflow Protection
  • Saturation
  • Bit-field Extract, Set, Clear
  • Bit Counting
  • Normalization
• 32-bit Address Range
• .18 micron / 5-level metal process
  (TI Timeline™ Technology)

VelociTI is a trademark of Texas Instruments