MISCELLANEOUS
Q: What is a delayed instruction?
A: A delayed instruction is when the final result has a latency of the
number of delay slots. (i.e. the multiply has 1 delay slot associated with
it and thus it will write the output two-cycles after the execution of the
instruction.)
Q: Will delay slots diminish the performance of the 'C6201?
A: No. Delay slots actually help performance levels. This is because
pipelining with delay slots allows for single-cycle throughput. In other
words, you can perform two multiply's every cycle (using both M functional
units). In non-pipelined DSPs, you would have had to wait until the multiply
is done before another multiply is allowed to start, causing every
instruction to be as slow as the slowest executing instruction (e.g. speed
would drop by half due to the multiply requiring more time). With
pipelining, this can be completely avoided allowing an effective
single-cycle throughput with a 5 ns clock cycle.
Q: What does MIPS stand for?
A: MIPS stands for millions of instructions per second. Current DSPs have
only been able to provide up to 120 MIPS. Due to the execution of eight
instructions per cycle in parallel at 200Mhz, the 'C6201 achieves 1600 MIPS
performance.
Q: Will there be industrial and military temperature versions of the 'C6x devices?
A: Yes. Industrial and military temperature versions of the 'C6201 are planned to be available in late 1997 or early 1998, after the commerical version achieves full TMS status.
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