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TMS320C67x
Digital Signal Processors
Leading performance with the VelociTI™ architecture
Traditionally, the advantages associated with VLIW architectures were often difficult to obtain. A lack of sophisticated code developmnet tools often meant that programmers were required to spend many hours optimizing code for performance, only to find these optimizations were largely negated by cumbersome and unwieldy code sizes.
The 'C6000 generation eliminates these drawbacks with the highly parallel and independent VelociTI architecture that emphasizes software-based flexibility through the industry's most efficient C compiler and the industry's first Assembly Optimizer. For designers, the direct translation is faster time-to-market with highly integrated and differentiated products.
The 'C67x core's performance is a product of a highly deterministic architecture that yields maximum code performance. The 167 MHz device delivers up to 1 GFLOP performance, which allows designers to replace multiple devices with a single DSP, increase the number of channels per DSP, and reduce system costs and development costs. In fact, the 'C6701 is so powerful that it is capable of reducing performance costs from dollars to dimes per MFLOP.
TI achieves this breakthrough floating-point performance by adding floating-point instructions to six of the 'C6000 architecture's eight functional units. These functional units, which are highly orthogonal, provide the compiler and Assembly Optimizer with many execution resources. Eight 32-bit RISC-like instructions are fetched by the CPU each cycle. VelociTI's instruction packing feature allows these eight instructions to be executed in parallel, serially or in parallel/serial combinations.
The 'C67x core also features byte addressability, a 32-bit address reach, 8-bit overflow protection, saturation, bit counting and normalization. In addition, all instructions are conditional, reducing costly branching and increasing parallelism for higher sustained performance.
Finally, the 'C6701 floating-point version of the 'C6000 core provides two banks of x16-organized memory, supporting double word load on each side of the CPU.
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