Executive Summary
Device Features
'C62x Architecture
'C62x EVM 
Device Specifications
Development Tools
Technical Documentation
TMS320C62x Third Parties
TMS320C62x Q&A
  Ask the 'C6x Experts
TMS320C62x Training
  Schedules for Europe
  and North America
TMS320C62x Assembly Benchmarks
TMS320C6000 Home

By providing 1600 MIPS performance, the TMS320C62x DSP transports the world of data- and telecommunications into an entirely new era, providing dramatic improvements for an entire new class of products.

The TMS320C62x generation gets its extraordinary processing power, ease-of-use and reduced cost from it's VelociTI™ Very Long Instruction Word (VLIW) architecture. VelociTI consists of multiple execution units running in parallel to perform multiple instructions during a single clock cycle. This level of parallelism is the key to extremely high performance at extremely low cost, taking the 'C62x DSPs well beyond the performance capabilities of traditional superscalar designs.

TMS320C62x Generation Key Features:

• 1600 MIPS and 200 MHz (5 ns instruction cycle time)
• Advanced VelociTI VLIW architecture that enables sustained throughput of up to eight instructions in parallel
• Industry's most advanced DSP C compiler
• Assembly Optimizer efficiently schedules tasks for amximum performance and ease in assembly language program
• Eight independent functional units
• New development paradigm based on software, not hardware
• 'C62x DSPs use RISC-like instructions, which facilitate mapping to multiple funtional units for additional scheduling flexibility
• Innovative instruction packing techniques
• Reduced development time and system cost by 50 percent with new generation tools designed for greatest ease of use and maximum optimization. These new tools include an extremely efficient C Compiler, providing 3x efficiency of existing compilers and the industry's first Assembly Optimizer.

Device Features

TMS320C6201

• 1600 MIPS and 200 MHz (5 ns instruction cycle time)
• VelociTI VLIW architecture
• Allows up to eight 32-bit instructions to be executed per cycle
• Large on-chip memory (512k bits Program and 512k bits Data) for fast algorithm execution
• 32-bit external memory interface supports SDRAM, SBRAM, SRAM
• 16-bit host port
• Four direct memory access (DMA) channels with bootloading capability
• Two multi-channel buffered serial ports for simplified interface to telecommunications trunks and interprocessor communication
• Two 32-bit timers
• 2.5V CPU with 3.3V Peripherals
• Pipelining of critical speed paths such as multiply, memory access and decode
• Power down support
• Optimized toolset
• Ultra-thin 352-lead ball grid array (BGA) package

Key Applications:

TMS320C62x DSPs energize existing multi-channel and multi-function applications:

• Wireless base stations
• Pooled modems
• Cable modems
• Remote Access Servers (RAS)
• Digital Subscriber Loop (xDSL) systems
• High-performance telephony
• Multi-media systems
• Multi-peripheral applications
• Wireless PDAs

• Unlimited Internet bandwidth and shorter download times
• Universal unplugged communication
• Ultimate cruise control with GPS and collision avoidance
• Personal home security
• Radical new telephone features
• Redefined medical diagnostics