C PROGRAMMING
Q: Will the 'C6000 C compiler be ANSI C compatible?
A: Yes. All TMS320 C compilers are ANSI C compatible.
Q: Will I be able to mix C and Assembly?
A: Yes. The development tools are designed to encourage the combination of C and assembly. Even though the C compiler provides up to 80% efficiency when
compared to handcoded assembly, some assembly programming may be required to
achieve maximum performance in some cases. Fortunately, the new profiler
will inform you about areas where performance may be improved by writing
assembly code. If desired, this assembly code can even be written serially
and then run through the Assembly Optimizer to parallelize the assembly for
optimal performance.
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APPLICATIONS
Q: Is the 'C6201 focused towards any particular applications, and what are
some possibilities for new applications?
A: Yes. The ability to perform multiple tasks simultaneously will allow one
'C6201 to process multiple channels of data. Until now, processing multiple
channels required multiple DSPs. This will reduce system cost significantly
by reducing the chip count. See the list of a few 'C62x applications
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HARDWARE
Q: What type of architecture is used in the 'C6201?
A: The 'C6000 DSPs use TI's VelociTI™ architecture. The VelociTI
architecture is an advanced VLIW architecture that is deeply pipelined to
allow multi-instruction, single-cycle execution. For more information on the
architecture, see the 'C6000 Technical Brief.
Q: What types of geometries were used in the 'C6201?
A: The 'C6201 uses a 0.25 micron technology with a 5 level metal process. The CPU has approximately 270,000 transisters. Future 'C6000 devices are
planned to incorporate 0.18 micron technology.
Q: What peripherals are on the 'C6201?
A: The 'C6201 will feature:
- 1 Mbit On-Chip RAM
- External Memory Support For SDRAM, SRAM, and SBSRAM
- 4-Channel Bootloading DMA
- 16-Bit Host Access Port
- 2 Enhance Buffered (T1/E1) Serial Ports (EBSPs)
- 2 32-Bit Timers
For more information, see the list of 'C6201 Features
Q: What is the typical power dissipation of the 'C6201?
A: In many simulations, the core at 200Mhz is expected to be below 3/4 Watt. The chip with memory and perpherals performing a typical application such as an FIR filter is expected to consume less than 5 watts. When comparing
power/performance, it will be comparable to other DSPs.
Q: What is the pricing of the 'C6201?
A: The suggested resale pricing of the TMS320C6201 is US $96 in 25K unit
quantities.
Q: When will the 'C6201 be ready for market?
A: The current schedule for the TMS320C6201 is as follows:
- Functional Samples available now
- Full-speed samples w/ additional peripherals in 2Q97
- Production version in 3Q97
Q: What are the key features of the pipeline?
A: The 'C6201 has a seven-cycle pipeline. The fetch has four stages, the
decode has two stages, and the Execute has one stage with up to five delay
slots. For more information on the pipeline, see the chapter on pipleline in
the CPU Instruction Set and Reference Guide.
Q: Why is the 'C6201 so deeply pipelined?
A: There are many benefits of deep pipelining. Some of these include:
Single-cycle throughput, ease and scalablility of memory interface, and
improved compiler target.
Q: What type of external memory interface will be on the 'C6201?
A: It will be a 32-bit memory interface operating at 200Mhz.
Q: What is the package for the 'C6201?
A: The 'C6201 will use a 352-lead Ball Grid Array package (BGA).
Q: What socket should be used with the 'C6201 for initial prototyping? Where can I get these?
A:A 352-lead BGA Socket should be used. These sockets can be obtained from companies such as Aries, Yamaichi, and Plastronics.
Q: What is the operating voltage(s) of the 'C6000 DSPs? Will I have to supply more than one voltage supply?
A: The 'C6201 will operate at 2.5v with a 3.3 volt I/O. Yes, two power supplies will be needed.
Q: Will the 'C6000 devices have JTAG boundary scan?
A: Yes. The 'C6000 devices have a pure JTAG interface which supports
boundary scan.
Q: Will the 'C6201 be available in die form? If yes, when?
A: The 'C6201 is planned to be available in die form after the device has
completed the Texas Instruments internal qualifications process, currently scheduled for late 3Q97.
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TOOLS
Q: When will the tools for the 'C6201 be ready? What platforms will be
supported?
A: The tools are available now, and support both the PC and SUN platforms. For more information on 'C6000 tools, see the 'C6000 tool features
Q: What new features are included in the 'C6000 toolset?
A: Several changes have been made to improve ease-of-use in the 'C6000
toolset. A new GUI interface was added to the Debugger and Profiler, which
allows much greater flexability in a Windows-type environment. The new C
compiler is the most efficient DSP compiler ever, with up to 80 percent
efficiency when compared to hand-coded assembly. Finally, the new Assembly
Optimizer takes advantage of the VelociTI advanced VLIW archetecture to
optimally parallelize assembly code.
Q: What is the pricing for the development tools?
A: The suggested resale pricing for the 'C6000 Simulator is US $495 (PC
version) and US $995 (SPARC version). The C Compiler, Assembly Optimizer,
and Linker is US $2,495 (PC version) and US $3,995 (SPARC).
Q: Is TI planning a 'C6000 DSP Starter Kit (DSK)?
A: We are currently evaluating the possibility of a DSK-type development tool for the 'C6000.
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PERFORMANCE
Q: What type of performance can I expect from the 'C6201?
A: One example is the Radix 2 FFT, where the average is 1600 MIPS
performance at 200 MHz. Another example is the FIR filter, where we reach
400 MACS performance. The same performance is reached in the dot product with
a single-cycle loop.
Q: How fast can the 'C6201 perform an FFT?
A: The 'C6201 can perform a 1,024 pt. FFT in less than 70 microseconds, or a 256 pt. FFT in less than 14 microseconds.
Q: Can you provide performance benchmarks for the 'C6201?
A: Performance benchmarks will be placed on our web-page as they become available.
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MISCELLANEOUS
Q: What is a delayed instruction?
A: A delayed instruction is when the final result has a latency of the
number of delay slots. (i.e. the multiply has 1 delay slot associated with
it and thus it will write the output two-cycles after the execution of the
instruction.)
Q: Will delay slots diminish the performance of the 'C6201?
A: No. Delay slots actually help performance levels. This is because
pipelining with delay slots allows for single-cycle throughput. In other
words, you can perform two multiply's every cycle (using both M functional
units). In non-pipelined DSPs, you would have had to wait until the multiply
is done before another multiply is allowed to start, causing every
instruction to be as slow as the slowest executing instruction (e.g. speed
would drop by half due to the multiply requiring more time). With
pipelining, this can be completely avoided allowing an effective
single-cycle throughput with a 5 ns clock cycle.
Q: What does MIPS stand for?
A: MIPS stands for millions of instructions per second. Current DSPs have
only been able to provide up to 120 MIPS. Due to the execution of eight
instructions per cycle in parallel at 200Mhz, the 'C6201 achieves 1600 MIPS
performance.
Q: Will there be industrial and military temperature versions of the 'C6000 devices?
A: Yes. Industrial and military temperature versions of the 'C6201 are planned to be available in late 1997 or early 1998, after the commerical version achieves full TMS status.
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