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TMS320C62x
Digital Signal Processors
Breakthrough VelociTI™ Architecture Means Unparalleled High Performance
Traditionally, the advantages associated with VLIW architectures were often difficult to obtain. A lack of sophisticated code generation tools often meant that programmers were required to spend many hours optimizing their code for performance only to find these optimizations were largely negated by cumbersome and unwieldy code sizes.
The ’C6000 platform eliminates these drawbacks with the highly parallel and independent VelociTI
architecture that emphasizes software-based flexibility through the industry’s most efficient C
compiler and the industry’s first Assembly Optimizer. For designers, the direct translation is faster time-to-market with highly integrated and differentiated products.
The ’C62x core’s performance is a product of a highly deterministic architecture that enables
maximum code performance. The 200 MHz device outperforms the competition with more than 1600
million instructions per second (MIPS) and 400 million multiply-accumulates (MMACs) per second.
The advent of such a high-performance DSP significantly lowers costs for manufacturers. As an example, a single TMS320C6201 can implement 30 vocoder channels at $3-per-channel in a wireless base station. Previous generation DSPs could only implement five channels at $7-per-channel. In a typical RAS application, a single ’C6201 can support 10-15 V.34 modems at a cost of about $9 per modem. Current high-end DSP-based systems only achieve one modem per DSP at about $18 per modem.
The eight functional units of the ’C62x core, which include two multipliers and six arithmetic
units, are highly orthogonal, pro-viding the compiler and Assembly Optimizer with many execution
resources. Eight 32-bit, RISC-like instructions are fetched by the CPU each cycle. VelociTI’s
instruction packing feature allows these eight instructions to be executed in parallel, serially, or in parallel/serial combinations. This optimized scheme enables significant reductions in code size, program fetches and power consumption.
Other features of the ’C62x core that contribute to its leading performance include byte
addressability, a 32-bit address reach, 8-bit overflow protection, saturation, bit counting and
normalization. In addition, all instructions are conditional, reducing costly branching and
increasing parallelism for higher sustained performance.
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