TMS320LC57 Features

The TMS320C57 incorporates the same amount of on-chip memory as the 'LC56 and offers a high-throughput buffered serial port (BSP). In addition, the 'LC57 provides an 8-bit wide host port interface (HPI) which can be used to communicate with other 'LC57 devices or embedded microprocessors. The 'LC57, like the 'LC56, is capable of 25-ns instruction cycle time at 3.3 V.

The TMS320LC57 features:

• 25- and 35-ns instruction cycle times at 3.3 V
• Boot load through HPI or standard serial port
• 192K-word external address reach
• Accepts source code from the 'C1x/'C2x/'C2xx generations
• ANSI C compiler
• IEEE 1149.1-standard (JTAG) emulator control
• Boot ROM option
• Full-duplex synchronous serial port
• Programmable PLL
• Buffered serial port with dedicated bus
• Host port interface with dedicated bus
• 128-pin TQFP package

TMS320LC57/'BC57S Host Port Interface

The host port interface (HPI) is an 8-bit parallel port available on the TMS320LC57 and the TMS320BC57S. The HPI provides a glueless interface to standard microprocessors as well as to other TI devices. The HPI appears as a 2K-word block of shared memory that is available in either a FIFO or standard random-access configuration. Most importantly, the HPI has the ability to maintain its high level of functionality as the interface between an external CPU and the 'C57, even while the 'C57 is idle or in reset. This significantly reduces system power consumption by offloading standard I/O tasks from the DSP.

Features of the HPI include:

• Byte-wide register addressability
• 8-bit parallel port
• High-speed back-to-back accesses
• Dedicated bus to a 2K 16-bit words of SARAM
• Shared-Access Mode (SAM)
  • Normal mode of operation
  • Allows DSP and host to have HPI memory access
  • Asynchronous host accesses are resynchronized internally
  • 45.7 Mbps at 57 MHz
  • 64.0 Mbps at 80 MHz
• Host-Only Mode (HOM)
  • Allows host to access HPI memory while 'C57 is in IDLE2 or in reset mode
  • 5 mA power dissipation (IDLE2)
  • 160 Mbps, independent of clock

TMS320LC56/'LC57/'BC57S Buffered Serial Port

The buffered serial port (BSP) provides a no-overhead mechanism to interface serially with CODECs, ADCs, and other peripherals. The BSP supports 8-, 10-, 12-, and 16-bit serial data packets and uses a 2K-byte buffer to hold input or output data. Downward code compatible with the standard serial ports, the BSP is designed to be completely flexible and programmable. The BSP has the ability to simultaneously receive data from and transmit data to a programmable on-chip buffer via a dedicated memory bus, freeing the CPU to execute other tasks without memory bus contention.