TMS320C5x FeaturesThe TMS320C5x generation of digital signal processors from Texas Instruments, with its unparalleled combination of performance, affordability, integrated memory choices and power-management features, has become the new 16-bit DSP standard. By offering 50-MIPS performance at 5V and 40-MIPS performance at 3V, flexible power-down modes for the lowest possible power consumption and a wide variety of integrated RAM and ROM combinations, TI makes it easy to select a 'C5x DSP that is right for your specific application. A TMS320C5x DSP Starter Kit (DSK) is now available for a suggested resale price of U .S. $99, allowing designers and beginners to break into the world of real-time digital signal processing. The DSK includes a TMS320C50-40 MHz-based board, assembler, debugger, loader, samples, user's guides, 'C5x EVM product brief and a coupon toward the purchase of the 'C5x EVM.
'C5x Key specifications
'C5x Key applications
Features By DeviceTMS320C5x Multiplier/ALU Features
The performance and parallelism of the 'C5x architecture become
evident by studying the multiplier and accumulator sections of
the device. The on-chip multiplier performs a 16-bit ´
16-bit multiply with a 32-bit product in a single cycle. To double the performance, the 'C5x devices can fetch two data operands when executing the multiply and accumulate (MAC) instruction.
Scaling and fractional math shifts occur in parallel with all
arithmetic operations.
The 'C5x devices are the first to include an accumulator buffer.
The accumulator buffer provides quick comparisons to the accumulator
contents to determine the minimum or maximum in a table of values,
a common operation for both general-purpose and DSP algorithms.
This is very useful in implementing Viterbi-decoding algorithms.
Additionally, the accumulator buffer allows quick temporary storage
of a commonly referenced value, which eliminates the extra cycles
it takes to store the value in memory. It also allows up to 65
bit shifts among accumulator, accumulator buffer, and carry.
Features of the TMS320C5x multiplier/ALU include:
TMS320C5x Parallel Logic Unit
The parallel logic unit (PLU) performs logical operations without
corrupting the ALU contents. This allows data to be checked and
decisions made without the overhead of storing and restoring the
ALU content.
The PLU supports AND, OR, XOR, and compare functions. These functions
are commonly used to set, clear, and toggle bits within a data-memory
location. To make these functions easy to use, dedicated instructions
perform them, using either immediate or register data to compare
with the data-memory location.
Features of the 'C5x PLU are:
TMS320C5x Interrupts
The TMS320C5x supports four external interrupts, two serial port
interrupts, one timer interrupt, and a trap instruction.
To speed up interrupt service routines (ISR), the key registers
are shadowed with a one-level deep stack and are saved in a single
cycle. This saves 22 cycles when an interrupt occurs by eliminating
the need to push and pop these 11 registers.
The TMS320C5x interrupt features include:
TMS320C5x Circular Addressing
Circular addressing is a method to address "aging" data
sets for common DSP algorithms. For example, after performing
the first set of calculations on an FIR filter data set, a new
data value must be brought in and the oldest value discarded.
DMOV allows you to do this by treating data in a circular fashion,
with the oldest and newest values located side by side. At the
end of each calculation, a new data value is placed in memory
at the location of the oldest value. You update the circular buffer
start address to correspond to the newest value and the circular
buffer end address to correspond to the oldest value.
Circular addressing features:
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