TMS320BC57S Features

The TMS320BC57S takes advantage of the same peripherals that are on the 'LC57 to make the 'BC57S a cost-effective embedded data I/O engine. In order to provide a broad-based appeal, the 'BC57S differs from the 'LC57 in four ways:

1) The 32K 16-bit words of ROM space has been replaced with a boot ROM

2) The 'BC57S can operate at 5 V

3) The 144-pin package of the 'BC57S has a wider lead pitch than the package of the 'LC57

4) The 'BC57S is lower in cost

Features of the TMS320BC57S include:

• 25-, 35-, and 50-ns cycle times at 5 V
• Standard boot loader
• 7K-word RAM
• Boot load through HPI or standard serial port
• 192K-word external address reach
• Accepts source code from the 'C1x/'C2x/'C2xx generations
• ANSI C compiler
• IEEE 1149.1-standard (JTAG) emulator control
• Full-duplex synchronous serial port
• Buffered serial port with dedicated bus
• Host port interface with dedicated bus
• 144-pin TQFP package

TMS320LC57/'BC57S Host Port Interface

The host port interface (HPI) is an 8-bit parallel port available on the TMS320LC57 and the TMS320BC57S. The HPI provides a glueless interface to standard microprocessors as well as to other TI devices. The HPI appears as a 2K-word block of shared memory that is available in either a FIFO or standard random-access configuration. Most importantly, the HPI has the ability to maintain its high level of functionality as the interface between an external CPU and the 'C57, even while the 'C57 is idle or in reset. This significantly reduces system power consumption by offloading standard I/O tasks from the DSP.

Features of the HPI include:

• Byte-wide register addressability
• 8-bit parallel port
• High-speed back-to-back accesses
• Dedicated bus to a 2K 16-bit words of SARAM
• Shared-Access Mode (SAM)
  • Normal mode of operation
  • Allows DSP and host to have HPI memory access
  • Asynchronous host accesses are resynchronized internally
  • 45.7 Mbps at 57 MHz
  • 64.0 Mbps at 80 MHz
• Host-Only Mode (HOM)
  • Allows host to access HPI memory while 'C57 is in IDLE2 or in reset mode
  • 5 mA power dissipation (IDLE2)
  • 160 Mbps, independent of clock

TMS320LC56/'LC57/'BC57S Buffered Serial Port

The buffered serial port (BSP) provides a no-overhead mechanism to interface serially with CODECs, ADCs, and other peripherals. The BSP supports 8-, 10-, 12-, and 16-bit serial data packets and uses a 2K-byte buffer to hold input or output data. Downward code compatible with the standard serial ports, the BSP is designed to be completely flexible and programmable. The BSP has the ability to simultaneously receive data from and transmit data to a programmable on-chip buffer via a dedicated memory bus, freeing the CPU to execute other tasks without memory bus contention.