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TMS320C54x Features
Port
Optimized CPU architectureThe high performance levels of the TMS320C54x DSPs are made possible by an innovative architecture designed to meet the needs of a variety of applications reduces Viterbi “butterfly update” down to only four instruction cycles for GSM channel decoding. This frees MIPS so the device CPU can perform other telephony system tasks.In addition to the Viterbi accelerator, other key features include:
Power-down modes for ultra-low powerTMS320C54x DSPs feature three power-down modes which are critical for power-sensitive systems. They are executed by the IDLE1, IDLE2, IDLE3 instructions. In these modes, the ’C54x DSP enters a dormant state and dissipates considerably less power than in normal operation. The core CPU shutdown sequence is activated when the IDLE1 instruction is executed.However, the system clock remains applied to the peripheral modules. The IDLE2 instruction shuts down the core CPU and peripheral modules, while IDLE3 is used for a complete shutdown of the processor. Millwatts per function - the true measure of power dissipation Processing capability in terms of MIPS is important but, due to differences in DSP architecture, MIPS data on one processor may not be as powerful as MIPS data on another processor. When a DSP executes a task more efficiently, designers are able to use remaining MIPS to implement tasks normally handled by off-chip ASICs or microcontrollers. This integration not only yields space savings, but power savings as well. Also, when a DSP task can be done more efficiently, the DSP can spend more time in power-down, or IDLE, mode. Thus, milliwatts per function—a measurement that comprehends the MIPS differences between architectures—is the most accurate and definitive way to measure power dissipation. The TMS320C54x DSPs feature three IDLE modes, low voltage operation down to 2.5 V at full performance, and an advanced architecture to efficiently implement wireless communication system tasks. For example, the TMS320C54x DSPs take only an average of 12.7 MIPS to implement full-rate GSM, 26.2 MIPS to implement half-rate GSM, only 2.3 MIPS for the Full-Rate GSM Speech Codec, and only 12.8 MIPS for IS-54/136 VSELP. Putting this into perspective of milli-watts per function—IS-54/136 VSELP requires only 31.1 mW, and the GSM Speech Codec only 5.6 mW of dissipated power. Clearly, the efficiency of the TMS320C54x architecture enables TI to provide the lowest milliwatts per function capability for the wireless communications market. Buffered serial portsAn auto-buffered serial port (BSP) provides read-write capability to a 2K-word data buffer, significantly lowering the processor’s overhead. The BSP can buffer up to 2K data samples before the CPU processes the stored data. The maximum throughput of the BSP is 50 Mbits/sec at a 20-ns instruction cycle. The BSP can operate at full-speed even while the CPU is in IDLE mode.Multi-channel Buffered Serial PortThe Multi-Channel Buffered Serial Port (MCBSP) is a superset of the BSP. The MCBSP enables full-duplex, bi-directional communication and direct interface to T1/E1 framers or H.100 telephony standards. It supports multi-channel transmit and receive up to 128 channels and data sizes from 8 bits to 32 bits.
6-channel DMA controllerThe six-channel DMA controller offers added flexibility and enhances performance. The DMA allows the peripherals to operate independently of the CPU and can facilitate program overlays, maximizing the overall efficiency of the device.
Host port interfaceA host port interface (HPI) provides a glueless interface to standard microprocessors as well as other TI devices. The HPI has the ability to maintain its high level of functionality as the interface between the host CPU and the ’C54x, even while the internal processor is idle.Ultra-thin packagingThe ’C54x generation allows systems to reduce chip count to lower system cost or increase functionality with fewer physical components. The ultra-small physical size of the ’C54x microStar ball grid array (BGA) packaging can also help increase the performance per square inch for MIPS intensive or space constrained applications.
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