TMS320C24x DSPs
TMS320C20x DSPs |
A manufacturer's ability to build high-performance products at a low cost can be a significant source of competitive advantage. With the introduction of four new devices and the best price-to-performance ratio in the industry, TI's powerful and cost-effective TMS320C2xx generation of DSPs is giving designers of high-volume applications in nearly every industry better ways to implement their systems. 'C2xx DSPs give designs historically implemented with 8-, 16- or 32-bit microcontrollers more processing power for added features, an easy-to-use development environment and wide ranging system flexibility with numerous peripherals. In addition, the highly integrated 'C2xx DSPs deliver cost savings at both the device and system levels over traditional solutions. The advantages of TI DSP Solutions are clear. Now, the 'C2xx generation is enabling manufacturers of price sensitive applications to cost-effectively implement the power of DSPs in their systems.
'C2xx generation devicesTI's 'C2xx generation features two main product groups -- 'C20x and 'C24x DSPs -- built upon the 'C2xLP core, with optimized peripheral mixes for specific market segments as well as general-purpose requirements.
'C2xx Block Diagram
Flash DSPsTogether, 'C20x and 'C24x DSPs represent the industry's first DSPs offering on-chip Flash memory, at a price that makes them viable for production systems. Available in 8-, 16- and 32-K-byte configurations, the large on-chip Flash enables designers to store the program code on-chip, eliminating the need for external memory. In-system reprogrammability provides an easy way to adapt to changing standards and make product upgrades with minimized time and reduced system development cost.To download Flash Utilities
'C2xx Memory BusThe 'C2xx advanced Harvard-type architecture maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. This multiple bus structure allows reading both data and instructions simultaneously. Instructions support data transfers between the two spaces. This architecture lets you store coefficients in program memory to be read in RAM,eliminating the need for a separate coefficient ROM. This, coupled with a 4-deep pipeline, allows the TMS320C2xx to execute most instructions in a single cycle. The 'C2xx dual-access RAM (DARAM) allows writes to and reads from the RAM in the same cycle without the address restrictions of SARAM. The dual-access RAM is configured in three blocks: block B0, block B1, and block B2. Block B0 is a 256-word block that can be configured as data or program memory. Block B1 is 256 words in data memory and block B2 is 32 words in data memory. The ability of the DARAM to perform two accesses in one cycle, coupled with the parallel nature of the 'C2xx architecture, enables the 'C2xx devices to perform three concurrent memory accesses in any given machine cycle. Various members of the 'C2xx generation have different memory mixes integrated on-chip. These can include additional single-access RAM, ROM, or Flash. |
Feature Phones