TMS320C2xx Features

'C2xx Key specifications

• Up to 36K words of on-chip memory lowers system cost by eliminating external memory
• Instruction Cycle Times of as little as 25 ns for increased performance
• Static design, power down modes, and PLL options for low-power dissipation
• Source code compatible with the 'C25 and upward compatible with TI's TMS320C5x generation
• Full complement of application-enabling peripherals
• Scan-based JTAG emulation

'C2xx Key applications:

• Feature-phones
• Digital Cameras
• Telecommunications Networks
• Hard-disk drives
• Point Of Sale Terminals
• Embedded Control

Features By Device

• TMS320C203
• TMS320F206
• TMS320C209
• TMS320C24x DSP controller

TMS320C2xx Synchronous Serial Port

The TMS320C2xx offers a full-duplex framed synchronous serial port with up to 20 Mbps throughput (@ 25-ns instruction cycle time). The transfer rate is one-half the device clockout rate. This bidirectional synchronous serial port provides direct communication with serial devices such as CODECs, serial ADCs, and other serial systems. The serial port can also be used for intercommunication between processors in multiprocessing applications.

Both the receive and transmit sides of the serial port have a 4-deep buffer or FIFO which allow the CPU to accept an interrupt at either 1, 2, 3, or 4 levels deep. This capability means less intervention from the CPU, as well as increased flexibility and efficiency with respect to data transfers.

The 'C2xx synchronous serial port features:

• Full-duplex framed synchronous serial port
• 4-word ´ 16-bit buffer to reduce interrupt service routine (ISR) overhead
• Serial port performance
  • 20 Mbps at 25 ns
  • 14.28 Mbps at 35 ns
  • 10 Mbps at 50 ns
• Transfer rate is 1/2 of CPU rate

All 'C2xx devices, except the 'C209, feature this serial port.

TMS320C2xx Asynchronous Serial Port

The TMS320C2xx offers an asynchronous serial port that is full-duplex and double-buffered. It accepts 8-bit data and can be programmed via a register to accept baud rates of up to 2.5 Mbps. The asynchronous serial port can be used to communicate with other devices such as microcontrollers or for RS-232 connections supporting data transfers of up to 115.2 Kbps.

Features included with the 'C2xx asynchronous serial port are:

• Full duplex
• Double buffered
• 8-bit data transfers
• 16-bit register for baud-rate generation
• Baud rates up to 2.5 Mbps (@ 25-ns instruction cycle time)

All 'C2xx devices, except the 'C209, feature this asynchronous serial port.

TMS320C203 Boot Loader

The 'C203 has an on-chip hard-coded boot loader, which allows you to load code from an 8-bit external EPROM into internal or external RAM. The EPROM is mapped into global data memory. Once the boot loading operation begins, 8-bit data is read by the device and reassembled into 16-bit words to a user-specified destination. When complete, control of the device is passed to the start of the program.

Features of the 'C203 boot loader are:

• Load from 8-bit external EPROM into internal/external RAM
• EPROM is mapped into global data memory space
• Dedicated boot loader pin
• Boot loader operation:
  • Reads 8-bit data
  • Reassembles into 16-bit words
  • Loads to user-specified destination
  • When complete, control passes to start of program

TMS320C2xx Memory Bus

The 'C2xx advanced Harvard-type architecture maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. This multiple bus structure allows reading both data and instructions simultaneously. Instructions support data transfers between the two spaces. This architecture lets you store coefficients in program memory to be read in RAM, eliminating the need for a separate coefficient ROM. This, coupled with a 4-deep pipeline, allows the TMS320C2xx to execute most instructions in a single cycle.

The 'C2xx dual-access RAM (DARAM) allows writes to and reads from the RAM in the same cycle without the address restrictions of SARAM. The dual-access RAM is configured in three blocks: block B0, block B1, and block B2. Block B0 is a 256-word block that can be configured as data or program memory. Block B1 is 256 words in data memory and block B2 is 32 words in data memory.

The ability of the DARAM to perform two accesses in one cycle, coupled with the parallel nature of the 'C2xx architecture, enables the 'C2xx devices to perform three concurrent memory accesses in any given machine cycle.

Various members of the 'C2xx generation have different memory mixes integrated on-chip. These can include additional single-access RAM, ROM, or Flash.