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TMS320C203 Features
The 'C203 features the core CPU of the 'C2xx generation and several
peripherals that optimize it for low-cost, high-volume applications.
The 'C203 has one synchronous serial port with a 4-deep FIFO,
which results in less intervention from the CPU, at a low cost.
There is also one full-duplex asynchronous serial port (UART),
a 16-bit timer, and a software wait-state generator.The serial
ports, timer, and wait-state generator are each mapped into I/O
space.
Features of the TMS320C203 include:
- 25-, 35-, and 50-ns instruction cycle times
- 192K-word external address reach
- Accepts source code from the TMS320C1x/'C2x generations
- ANSI C compiler
- 2, ´1, ´2,
and ´4 PLL options
- IEEE 1149.1-standard (JTAG) emulator control
- Available Boot loader
- Full-duplex synchronous serial port with 4-level-deep FIFO
- Full-duplex asynchronous serial port (UART)
- 100-pin TQFP package
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