TMS320C2x FeaturesThe TMS320C2x generation of Digital Signal Processors offers a rich choice of RAM, ROM, and OTP PROM versions, complemented by specific differentiating features. Also, the 'C2x is source code upward-compatible with first-generation 'C1x devices, but with performance of 10-12.5 MIPS capabilities of single-cycle, multiply accumulate with data move. Not only can first-generation designs migrate to second-generation devices, when more MIPS are required, an upgrade to the 20-50 MIPS capability of the fifth-generation TMS320C5x series is a simple matter. Because the TMS320C2x is the high-volume industry standard, more application software has been written for the 'C2x generation than for any other DSP. A library of proven application software plus a Digital Filter Design Package (DFDP) is available from TI, and a host of third party companies produce a wide range of 'C2x-based hardware and software products. A TMS320C2x DSP Starter Kit (DSK) is now available for a suggested resale price of U.S. $99, offering first-time users a low-cost tool for 'C2x device evaluation. Included with the kit is an assembler, debugger and a 'C26-based board, allowing designers and beginners to break into the world of real-time digital signal processing. Also included is a coupon toward the purchase of a 'C2x EVM. 'C2x Key specifications:
'C2x Key applications:
Features By DeviceTMS320C2x Multiplier/ALU Features
The performance and parallelism of the 'C2x-generation architecture
become evident by studying the multiplier and accumulator section
of the device.
Similar to the 'C1x generation, the on-chip multiplier performs
a 16-bit ´ 16-bit multiply with
a 32-bit product in a single cycle. However, to double the performance,
the 'C2x-generation devices can fetch two data operands when executing
the multiply and accumulate (MAC) instruction.
The 16-bit barrel shifter scales data in parallel with ALU operations;
data is shifted up to 16 bits during the same cycle it is used
in the ALU. The 0-, 1-, 4-, or 6-bit left shifter also operates
in parallel with the ALU to support both integer and fractional
math. Features of the 'C2x multiplier/ALU include:
TMS320C2x Interface to Off-Chip Devices
Internally, the 'C2x generation uses a modified Harvard architecture
with separate program and data buses to perform program and data
fetches in parallel. Externally, these buses are multiplexed together
to reduce package size and cost. Most applications place either
program or data in on-chip memory, with the other residing in
off-chip memory to minimize external bus conflicts and maximize
performance.
The proper strobe is selected by the processor based on whether
a program fetch, operand fetch, or I/O command is being executed.
These signals ease the interface to external memory and peripherals.
The READY line supports the addition of wait states for accessing
external memory. This is useful for low-cost systems that use
slow external memory to reduce cost yet maintain high performance
via on-chip memory. The (Hold) and (Hold Acknowledge) signals allow an external processor to stop execution, directly access the 'C25's
external memory, and resume execution. This is quite useful in
either designs with multiple 'C25s or systems that have a host
processor. A separate I/O select signal provides 16 I/O ports
using the 16-bit data bus. The I/O ports provide an easy interface
to ADCs and DACs, because the I/O ports have a separate select
signal in addition to the standard data bus interface signals.
The serial port provides a glueless interface to analog interface
circuits (AIC) such as the TLC320C44. The serial port is double-buffered
with separate transmit and receive circuitry, providing serial
transmission rates of up to 6.25 Mbps. Features of the 'C2x interface to off-chip devices include:
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