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TMS320C24x Features
With the TMS320C24x DSP Controllers, designers of digital control systems now have access to the industry's first single-chip DSP controllers specifically optimized for control applications. With the introduction of four new devices and the best price-to-performance ratio in the industry, TI's powerful and cost-effective 'C24x DSPs are giving designers of control applications better ways to implement their systems. These highly integrated devices represent a significant breakthrough over traditional microcontroller and general-purpose DSP processor solutions by enabling direct-drive, variable-speed control of simple-to-build brushless motors. These devices also provide better motor performance, lower energy usage, quieter operation, and greater reliability when compared to other solutions.
'C24x Applications 'C2xLP Core 'C24x Optmized Event Manager 'C24x Devices with Flash Memory 'C24x Serial Interfaces 'C20x/'C24x Memory Bus 'C24x Key Features:
'C24x Applications:
'C2xLP CoreThe 16-bit 'C2xLP core incorporates a static design and is manufactured in a sub-micron, triple-level-metal, full-complementary CMOS process for high-performance, low-power operation. The core was first available as a CPU option in TI's customizable DSP (cDSP™) design methodology, and was designed from the beginning to be combined with numerous complementary functions. TI's 'C2xLP core features two main product groups, 'C20x and 'C24x DSPs, with optimized peripheral mixes for specific market segments. The 'C24x DSPs are ideal for digital control system applications.
'C24 Block Diagram To complement the optimized 'C20x and 'C24x devices, TI also provides designers with a full range of mixed-signal and analog devices to simplify application development. Components include analog-to-digital (ADC) and digital-to-analog converters (DAC), operational amplifiers, voltage regulators, RS-232 transceivers and control area networking (CAN) transceivers. 'C24x Optmized Event Manager
Features include up to three up/down timers and up to nine comparators which, when coupled with flexible waveform generation logic, can create up to 12 PWM outputs. This design includes support for symmetrical (centered) and asymmetrical (non-centered) PWM generation capabilities, and a space vector PWM state machine. The PWM's dead-band generation unit is included and helps protect power transistors. In addition, the event manager integrates up to four capture inputs, two of which can serve as direct inputs for optical-encoder quadrature pulses. In all, these features represent a state-of-the-art solution for flexible PWM generation and system control. 'C24x Devices with Flash MemoryThe 'F240, 'F241 and 'F243 devices represent the industry's first DSP offering on-chip Flash memory, at a price that makes them viable for production systems. Available in 8- and 16- K-byte configurations, the large on-chip Flash enables designers to store the program code on-chip, eliminating the need for external memory. In-system reprogrammability provides an easy way to adapt to changing standards and make product upgrades with minimized time and reduced system development cost. Software utilities to program the Flash memory are also available.To download Flash Utilities 'C24x Serial Interfaces The TMS320x240 devices include a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard NRZ format. The SCI receiver and transmitter are double buffered, and each has it own separate enable and interrupt bits. Both may be operated independently or simultaneously in the full duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun and framing errors. The speed of the bit rate is programmable to over 65,000 different speed through a 26-bit baud select register.
The TMS320x240 devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high speed synchronous serial I/O port that allows a serial bit stream of programmed lenght (1 to 8) to be shifted into and out of the device at a programmable bit-transfer rate. The SPI normally is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers and ADCs. Multi-device communications are supported by the master/slave operation of the SPI.
'C20x/'C24x Memory BusThe 'C20x/'C24x advanced Harvard-type architecture maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. This multiple bus structure allows reading both data and instructions simultaneously. Instructions support data transfers between the two spaces. This architecture lets you store coefficients in program memory to be read in RAM,eliminating the need for a separate coefficient ROM. This, coupled with a 4-deep pipeline, allows the TMS320C2xx to execute most instructions in a single cycle.The 'C20x/'C24x dual-access RAM (DARAM) allows writes to and reads from the RAM in the same cycle without the address restrictions of SARAM.The dual-access RAM is configured in three blocks: block B0, block B1, and block B2. Block B0 is a 256-word block that can be configured as dataor program memory. Block B1 is 256 words in data memory and block B2 is 32 words in data memory. The ability of the DARAM to perform two accesses in one cycle, coupled with the parallel nature of the 'C20x/'C24x architecture, enables the 'C20x/'C24x devices to perform three concurrent memory accesses in any given machine cycle. Various members of the 'C20x/'C24x generation have different memory mixes integrated on-chip. These can include additional single-access RAM, ROM, or Flash. |
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