TMS320C20x Features
'C20x Key Specifications
'C20x Applications
'C2xLP Core
Features by Device
Flash DSPs
'C20x Enhanced Sychronous Serial Port
'C20x Asynchrous Serial Port
'C203 and 'LC203 Boot Loader
'C20x Memory Bus
- General-purpose DSPs with 20-40 MIPS
- Up to 32K words of on-chip memory (Flash or ROM) lowers system cost by eliminating the need for external memory
- Instruction Cycle Times of as little as 25 ns for increased performance
- Static design, power down modes, and PLL options for low-power dissipation
- Source code compatible with the 'C25 and upward compatible with TI's TMS320C5x generation
- Full complement of application-enabling peripherals
- Scan-based JTAG emulation
- Suite of easy-to-use development tools available
High-volume, emerging consumer, telephony, industrial and consumer applications like:
- Feature-phones
- Digital Still Cameras
- Telecommunications Networks
- Hard-disk drives
- Point Of Sale Terminals
- Embedded Control
The 16-bit 'C2xLP core incorporates a static design and is manufactured in a sub-micron, triple-level-metal, full-complementary CMOS process for high-performance, low-power operation. The core was first available as a CPU option in TI's customizable DSP (cDSPä) design methodology, and was designed from the beginning to be combined with numerous complementary functions. TI's 'C2xLP core features two main product groups, 'C20x and 'C24x DSPs, with optimized peripheral mixes for specific market segments. The 'C20x DSPs are ideal for telephony and consumer applications.
'C20x Block Diagram
To complement the optimized 'C20x and 'C24x devices, TI also provides designers with a full range of mixed-signal and analog devices to simplify application development. Components include analog-to-digital (ADC) and digital-to-analog converters (DAC), operational amplifiers, voltage regulators, RS-232 transceivers and control area networking (CAN) transceivers.
Together, 'C20x and 'C24x devices represent the industry's first DSPs offering on-chip Flash memory, at a price that makes them viable for production systems. Available in 8-, 16- and 32-Kbyte configurations, the large on-chip Flash enables designers to store the program code on-chip, eliminating the need for external memory. In-system reprogrammability provides an easy way to adapt to changing standards and make product upgrades faster and more economically. Software utilities to program the Flash memory are also available.
The TMS320C20x DSPs offer a full-duplex framed enhanced synchronous serial port (ESSP) with up to 20 Mbps throughput (@ 25-ns instruction cycletime). The transfer rate is one-half the device clockout rate. This bidirectional synchronous serial port provides direct communication with serial devices such as CODECs, serial ADCs, and other serial systems. The ESSP can also be used for intercommunication between processors in multiprocessing applications.
Both the receive and transmit sides of the ESSP have 4 level FIFOs which allow the CPU to accept an interrupt at either 1, 2, 3, or 4 levels deep. This capability means less intervention from the CPU, as well as increased flexibility and efficiency with respect to data transfers.
The 'C20x ESSP features:
- Full-duplex, double-buffered Synchronous Serial Port
- Highly Flexible Operation:
- Burst and Continuous modes
- Supports 8- and 16-bit word lengths
- Multi-channel mode with glueless interface to as many as four voice-band or telephony
codecs for telecommunications applications such as line cards.
- Serial Peripheral Interface (SPI) mode
- Independent four-level deep FIFO for both the receive and transmit sections
- Programmable FIFO level interrupts to reduce software overhead
- FIFO level status bits
- Various clocking options to ease interfacing in many applications
- Internal shift clock, CLKX, derived from an independent 8-bit pre-scalar
- Internal frame sync, FSX, derived from an independent 8-bit pre-scalar
- Polarity control on shift clock, CLKX, and frame sync pulse, FSX
- High immpedance control on data transmit pin DX for TDM applications
- Pre-scalars are configuarable as a general-purpose 16-bit counter
- Fast Transfer Rate:
- 20 Mbits/s at 25ns cycle time
All 'C20x devices, except the 'C209, feature this serial port.
The TMS320C20x offers an asynchronous serial port that is full-duplex and double-buffered. It accepts 8-bit data and can be programmed via a register to accept baud rates of up to 2.5 Mbps. The asynchronous serial port can be used to communicate with other devices such as microcontrollers or for RS-232 connections supporting data transfers of up to 115.2 Kbps.
Features included with the 'C20x asynchronous serial port are:
- Full duplex
- Double buffered
- 8-bit data transfers
- Auto baud detect feature
- 16-bit register for baud-rate generation
- Baud rates up to 2.5 Mbps (@ 25-ns instruction cycle time)
All 'C20x devices, except the 'C209, feature this asynchronous serial port.
The 'C/'LC203 has an on-chip hard-coded boot loader,which allows you to load code from an 8-bit external EPROM intointernal or external RAM. The EPROM is mapped into global datamemory. Once the boot loading operation begins, 8-bit data isread by the device and reassembled into 16-bit words to a user-specifieddestination. When complete, control of the device is passed tothe start of the program.
Features of the 'C203 boot loader are:
- Load from 8-bit external EPROM into internal/external RAM
- EPROM is mapped into global data memory space
- Dedicated boot loader pin
- Boot loader operation:
- Reads 8-bit data
- Reassembles into 16-bit words
- Loads to user-specified destination
- When complete, control passes to start of program
The 'C20x/'C24x advanced Harvard-type architecture maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. This multiple bus structure allows reading both data and instructions simultaneously. Instructions support data transfers between the two spaces. This architecture lets you store coefficients in program memory to be read in RAM,eliminating the need for a separate coefficient ROM. This, coupled with a 4-deep pipeline, allows the TMS320C2xx to execute most instructions in a single cycle.
The 'C20x/'C24x dual-access RAM (DARAM) allows writes to and reads from the RAM in the same cycle without the address restrictions of SARAM.The dual-access RAM is configured in three blocks: block B0, block B1, and block B2. Block B0 is a 256-word block that can be configured as dataor program memory. Block B1 is 256 words in data memory and block B2 is 32 words in data memory.
The ability of the DARAM to perform two accesses in one cycle, coupled with the parallel nature of the 'C20x/'C24x architecture, enables the 'C20x/'C24x devices to perform three concurrent memory accesses in any given machine cycle.
Various members of the 'C20x/'C24x generation have different memory mixes integrated on-chip. These can include additional single-access RAM, ROM, or Flash.
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