1600 MIPS DSP 'C6201 unleashes highest level of DSP price/performance 'C6x development tools emphasize software techniques New VelociTI architecture key for parallel performance Industry perspectives on the 'C6x 1997 TMS320C6x technical training

’C6x development tools emphasize software techniques Intimate knowledge of DSP architecture is no longer necessary to get maximum code performance To support the industry’s most powerful line of DSP Solutions, TI has introduced an equally powerful development environment. The easy-to-use ’C6x tool set allows software engineers to write applications in high-level C code, and even write critical sections in assembly language, all without concern for the mechanics of the underlying processor architecture. The optimization capabilities of the C compiler and the unique new Assembly Optimizer produce highly efficient code without time-consuming hand optimization. Even designers with little DSP experience or understanding of the underlying architecture can be very productive in a short time. The result is faster time-to-market for new applications by cutting software development time in half. As the architectures of the TMS320 DSP family have developed more parallelism and deeper pipelining, compiler technology has kept pace enabling ever faster application code execution. For the ’C6x, the new C compiler generates code providing a 3´ improvement in compiler efficiency over other fixed-point DSP compilers. Also, the advanced Very Long Instruction Word (VLIW) VelociTI architecture provides instruction-level parallelism that allows up to eight new instructions to be dispatched in every cycle. Parallel execution of many of these instructions, as organized by the C compiler and the Assembly Optimizer, is the key to the ’C6x’s unmatched code efficiency. For application development, the developer can use the ’C6x tools in a sequence to achieve the level of code efficiency required. As a first step, the code resulting from an initial compilation can be analyzed with dynamic profiling and cycle counting tools that are part of the development environment. The developer can then determine whether sufficient optimization has been achieved by the compiler’s optimization procedures - an outcome that would achieve the fastest time-to-market and lowest product development costs. As a next step, the developer can use several command-line options, a library of extremely fast functions, and some suggested programming techniques, all of which take advantage of the VelociTI architecture. The analysis tools can also help to determine whether the product can achieve its performance goals with minimal additional development time and cost. Finally, hot spots - critical program sections such as computationally-intensive software loops - can be written for the Assembly Optimizer in linear assembly, which does not require attention to parallel instructions, instruction latencies, or register usage. The Assembly Optimizer schedules the instructions honoring ’C6x latency requirements, maximizing parallel code, and allocating registers to produce an unrivaled level of code performance. Debugging efficiency is another significant factor in reducing time-to-market for new applications. The ’C6x development environment provides a new Windows-based Graphical User Interface (GUI) for debugging that is intuitive and user-friendly, yet fully compatible with existing TMS320 DSP debuggers. A dynamic profiler that helps users analyze code performance by identifying bottlenecks within the code is included. The complete ’C6x code generation development tool set is available now and includes the C compiler, Assembly Optimizer, and linker. US suggested resale pricing for the code generation tools is $2,495 (PC version) and $3,995 (SPARC). The ’C6x simulator is also available now at a suggested resale price of US $495 (PC), and $995 (SPARC). TI also plans to release a ’C6x test and evaluation board in 2Q97. This board will provide new debugger software that will allow the ’C6x to communicate with existing XDS510 emulators, so no new emulator will be required to use the test and evaluation board.