1600 MIPS DSP 'C201 unleashes highest level of DSP price/performance 'C6x development tools emphasize software techniques New VelociTI architecture key for parallel performance Industry perspectives on the 'C6x 1997 TMS320C6x technical training

’C6201 unleashes highest level of DSP price/performance Lowest cost per channel ever for communications systems The TMS320C6201, the most powerful general-purpose programmable fixed-point DSP ever built, is the first DSP in the industry to adopt TI’s new VelociTI(TM) architecture, an advanced Very Long Instruction Word (VLIW) implementation that delivers an unprecedented 1600 MIPS at 200 MHz. With its 5-ns cycle time, the ’C6201 can complete a 1,024-point complex Fast-Fourier Transform (FFT) in only 70 microseconds. The ’C6201 also incorporates innovative instruction packing techniques that reduce code size, program-fetch overhead, and power consumption, and the chip’s 100% conditional instructions reduce costly branching and increase parallelism for higher sustained performance. Key ’C6201 features include dual data paths from eight functional units including two multipliers and six arithmetic units allowing the chip to execute up to eight 32-bit instructions per cycle delivering up to 10 times the performance of previous DSPs. Other device features include 3.3-volt operation for I/O and 2.5-volt core operation, 16-bit multiplies, and 32-/40-bit arithmetic. The ’C6201’s memory and peripheral mix provides 1 Mbit of on-chip RAM (512K bits program, 512K bits data), and a 32-bit glueless external memory interface that supports SDRAM, SBSRAM, and SRAM. Two direct memory access (DMA) channels with bootloading capability provide efficient access to external memory and peripherals while minimizing CPU interrupts. A 16-bit host access port, two enhanced buffered serial ports (T1/E1), and two 32-bit timers complete the design. The ’C6201, packaged in an ultra-thin 352-lead ball grid array, represents entirely new levels of performance and savings for communications applications. In these applications, such as V.34 modems or wireless base stations, the ’C6201 can increase the number of communication channels per DSP or raise the throughput capacity of a single channel. For example, the ’C6201 can allow remote access server designers to provide more modems in less space. The power of a single ’C6201 can implement 10 to 15 V.34 modems at a cost of about US $6 per modem. Previous DSPs could only achieve one modem per DSP, at about US $18 per modem. For base stations, a single ’C6201 can implement 30 enhanced full-rate (EFR) voice channels at US $3-per-channel, versus five voice channels at US $7-per-channel for previous DSPs. Not only does the ’C6201 provide a 50 percent lower cost per channel, it also reduces chip count and system space. Now a 128-channel base station, which required up to 24 DSPs, can be implemented on four ’C6201s. US pricing for the 0.25 micron, five-level metal ’C6201 is $96 (25K units). An advanced-release version is now sampling, with a production release scheduled to begin sampling in 2Q97. Future ’C6x members, both fixed- and floating-point, will be disclosed throughout 1997 and beyond and will include devices using TI’s new 0.18-micron process, operating at speeds beyond 250 MHz.