TI has introduced a new 66 MIPS, 16-bit, fixed-point DSP that
increases the available performance of large on-chip RAM DSPs.
The TMS320LC548
combines high performance with low power consumption, making it
well suited for wireless telecommunications and other mobile systems
that need to perform complex functions while also conserving battery
power. Typical applications for the new device include digital
cellular base stations, wired and wireless telephones, mobile
radios, personal digital assistants (PDAs), and high-end applications
that merge digital telecommunications and networking, such as
private branch exchanges (PBXs), T1/E1 line cards, and other multimedia
and telephony systems with high-speed modem or Integrated Services
Digital Networks (ISDN) capabilities.
"The 'LC548 will offer twice the performance of the nearest
competitive fixed-point DSP, opening up new possibilities in high-performance
applications," said Ron Wages, TI's marketing manager for
DSP products. "With enhancements including the use of 0.25-micron
quad-level metal process technology, a streamlined architecture,
and increased clock speeds, the 'LC548 shows how we plan to achieve
100 MIPS for 16-bit fixed-point DSPs within a year."
Increased DSP performance allows systems to perform a variety
of processing functions on a single chip that today have to be
distributed. For example, a digital cellular basestation can handle
multiple full-duplex channels of vocoding and echo cancellation
with a single 'C54x DSP, minimizing system cost, space, and power.
Other applications include the ability to integrate V.34, digital
simultaneous voice data (DSVD), full-duplex speakerphone, FM and
wavetable synthesis, 3-D sound, and a variety of telephony algorithms
onto a 'C54x, creating a highly powerful, yet low-cost multimedia/telephony
platform.
The 'LC548 integrates 32K words of fast static random-access memory
(SRAM), essential to reconfigurable systems that need to frequently
swap code when switching among different tasks. For example, a
cellular base station might need to load new algorithms for dealing
with a variety of calls that conform to different cellular communications
protocols. The 'LC548 augments its own large on-chip SRAM with
the capability to address up to 4M words of external memory space,
allowing the device to access an enormous external memory pool.
The 'LC548 also features architectural enhancements that maximize
the performance achievable with C programming, simplifying software
development. Algebraic and mnemonic assemblers also make code
development easier.
Along with the fast CPU and large memory, the device integrates
peripherals functions, easing OEM product development and speeding
time to market through simplified design. Included are two high-speed
buffered serial ports, one time-division multiplexed serial port,
a host port interface, and a timer. Both buffered serial ports
and the host port interface have separate dedicated buses to the
on-chip memory that allows data transfers to occur even while
the CPU is in IDLE mode.
One version of the device will operate at 3.3 volts with 66 MIPS
performance ('LC548), another at 3.0 volts with 60 MIPS performance
('VC548). Sampling of the 66-MIPS version of the 'LC548 DSP is
planned for late in the third quarter of 1996, with volume production
planned for early 1Q97. Suggested resale production pricing is
US $35 (66 MIPS) at 50,000-piece quantities. The 144-pin thin
quad flatpack (TQFP) device will be available from TI and authorized
distributors worldwide. A pin-compatible device, the TMS320LC542,
is available now and can be used to begin 'LC548 designs.