Under construction

Major Dallas SC fab expansion increases DSP capacity

Texas Instruments has announced a $2 billion expansion in Dallas, Texas over the next 18-24 months that includes its largest ever semiconductor wafer fabrication facility, which will be primarily dedicated to production of TMS320 DSPs. The expansion also includes a new research and development facility.

"We are concentrating more than 90 percent of our semiconductor capital expenditures in high-growth, higher-margin areas such as digital signal processors, mixed signal/analog, and advanced logic products. The new R&D facility will enhance our efforts to design processes to manufacture the digital solutions of tomorrow," said Thomas J. Engibous, TI executive vice president and president, semiconductor group.

"Real-time" capacity

Initially, the new facility, DMOS 6 (Dallas metal-oxide semiconductor), will be equipped to produce approximately 10,000 eight-inch (200-mm) silicon wafers per month. As market demand increases, new equipment can be added in the existing space to increase output to about 30,000 wafers per month when the building is fully outfitted.

DMOS 6 will produce semiconductors with dimensions of 0.25-micron, but will eventually produce semiconductors with measurements as small as 0.12 micron. The new fab will contain more than 1 million square feet of space, including a 118,000 square-foot cleanroom. Total projected cost for the facility, including equipment, is approximately $1.6 billion. Volume production at the new facility is expected by the end of 1997.

R&D 1 construction

R&D 1, the new research facility, will be a state-of-the-art focal point for work in TI's core competencies of microelectronics, signal processing, and software. It will encompass 580,000 square feet, including a 51,000 square-foot cleanroom.

The facility will mainly be used for development of new semiconductor manufacturing processes that support 0.18-micron and 0.12-micron devices over the next few years. Eventually, a portion of the cleanroom will house TI's 12-inch (300-millimeter) development program for the next generation of silicon wafer manufacturing. Total cost of the project when complete, including equipment, is estimated at more than $300 million.

Completion of R&D 1 is scheduled for the second quarter of 1997. Equipment installation will begin early in 1997 with full operation of the cleanroom expected by the end of 1997.

Together, DMOS 6 and R&D 1 will rank as one of the world's cleanest and most environmentally-sensitive complexes. Systems inside the facilities will automatically clean exhaust systems, recycle water, reprocess chemicals and reduce energy consumption.

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