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Blue Band

New 'C57S provides cost-effective I/O engine

TI's offering of DSP solutions for embedded data and telecommunications applications has expanded with the announcement of a new peripheral-rich DSP, the TMS320C57S. The new device is a lower-cost version of TI's TMS320LC57 DSP, and is optimized for mass-market embedded applications such as mobile radios, navigational communications systems, cellular basestations, and networking equipment.

Integrating a high-performance 'C5x-series DSP CPU with 7K words of on-chip RAM, a zero-overhead buffered serial port (BSP), and a glueless host-port interface (HPI), the 'C57S facilitates processing of the large amounts of data I/O required for communications applications.

"While the 'C57S can operate at up to 40 MIPS, the power of its performance is greatly enhanced by the capabilities of the on-chip intelligent peripherals," said TI Fixed-Point DSP Applications Manager Jim Larimer.

With its own dedicated on-chip memory bus, the full-duplex, 40 Mbits/sec BSP improves system performance by eliminating the need for the DSP CPU to service real-time data-frame interrupts from system I/O peripherals such as codecs or A/D converters. Similarly, because operation of the independent 8-bit HPI incurs no DSP CPU loading, a direct interface between the 'C57S and standard host microprocessors or other DSPs is simplified.

  • Both 'C57S peripherals are fully functional even when the
  • 'C57S is in idle or reset mode, resulting in decreased system
  • power consumption. The combined processing and peripheral features of the 'C57S make it an ideal data I/O engine for any DSP application requiring high-speed serial transmission, host-processor communication, large amounts of on-chip code, and/or data.

    The 'C57S includes four new features not found on the 'LC57: 1) lower cost; 2) both 5- and 3.3-volt versions available; 3) on-chip bootloader; and 4) 0.5-mm lead pitch packaging. Various bootloader modes allow the 'C57S to boot from an 8-bit EPROM, the chip's standard serial port, or the HPI for a high degree of system-design flexibility.

    The 'C57S is available in a 144-pin TQFP with a 0.5-mm pitch in 40-MHz (20-MIPS), 57-MHz (28.5-MIPS), and 80-MHz (40-MIPS) versions from TI and its authorized distributors.

    The suggested resale price of the '40-MHz 'C57S is U.S. $24.25 each in 10,000-unit quantities. Sample devices are planned for the third quarter of 1995.


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