Texas Instruments broadened its programmable DSP offering for the telecommunications industry with the introduction this summer of the TMS320C57. The device's high level of integration, increased performance, and low-power operation make the new DSP well-suited for implementing the baseband functions of next-generation, portable digital cellular telephones. The new DSP also will allow advanced product features such as hands-free operation and ambient noise and acoustic echo cancellation in smaller, sleeker end-equipment designs.
The 'C57 includes sufficient on-board memory to implement digital cellular telephone standards (including IS-54, PDC, and GSM), and two new intelligent peripherals-a Buffered Serial Port (BSP) and a Host Port Interface (HPI).
TI has optimized the design of the 'C57 around its 3.0-volt CMOS process, making the device among the most power-thrifty in its class. This true 3-volt process allows the 'C57 to run at a sustained throughput of 40 MIPS at 3 volts.
In addition, this advanced process technology gives the 'C57 a roadmap to 2-volt performance. Lower currents coupled with lower voltage will result in extremely low power consumption for next-generation applications. With standby current as little as 5 mA, the device is ideal for portable telecommunications applications, including PCMCIA-based V.34 modems and personal digital assistants (PDAs), where long battery life is crucial.
The lower-cost TMS320C56 is also available for applications not requiring a host interface. Since the 'C57 and the 'C56 are both based on the standard TI 'C5x DSP core, system developers can speed their designs to market by making use of the entire array of standard 'C5x development tools, including C compilers, assemblers, linkers, simulators, and evaluation modules. These tools help system developers meet the critical time-to-market requirements for a growing worldwide digital cellular telephone market.
The 'C57 provides a larger combined ROM and RAM mix than any other TI 16-bit DSP, with 32K words of ROM, 7K words of RAM, the BSP, and the HPI.
"The smart peripherals on the 'C57 improve the DSP performance by allowing the device to spend a larger percentage of its available MIPS processing data instead of servicing system data requests," said John Cooper, marketing manager for TI's standard DSP products. "Since the BSP and the HPI are now standard peripherals in our 'C5x generation, their advanced functionality will also be available for use in other high-performance applications and in customizable DSPs."
The ROM/RAM mix also allows the device to be used in other applications that require design flexibility, including high-performance modems, multimedia, and personal digital assistants where the need to incorporate multiple functions, such as speech compression and speech recognition, is important.
The 'C57 is packaged in a 128-pin thin quad flat pack (TQFP), and the 'C56 is packaged in a 100-pin TQFP. Suggested high-volume direct pricing for the 'C57 and 'C56 is U.S. $37.60 and $34.20, respectively. Sample quantities of both are planned for fourth quarter 1994. Production availability is planned for second quarter 1995.