With a roadmap to 100-MIPS performance, the new TMS320LC548 DSP lets you integrate multi-chip solutions into a single chip. It also enables reconfigurable systems due to 32K words of on-chip SRAM with 4M word address range.

Features include:

• 50/66/80/100 MIPS
• 3-V operation
• 32K x 16 bits on-chip program/data RAM
• 3 serial ports, timer, and HPI
• 3 power-down modes
• 80% improvement in traditional C compiler efficiency

For more information, see:

TMS320C54x DSPs
TMS320C54x DSP Development Tools

TMS320 DSP Designer's Notebook pages:

Number 64 - Accessing TSM320C54x Memory-Mapped Registers in C-C54XREG.H (77.5KB)=20
Number 70 - Parity Generation on the TMS320C54x (130KB)=20
Number 71 - =B5-Law Compression on the TMS320C54x (75.6KB)=20

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