head     56.3;
access   paws bayes jws quist dew jwh;
symbols  ;
locks    ; strict;
comment  @# @;


56.3
date     93.01.27.13.53.20;  author jwh;  state Exp;
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56.2
date     93.01.27.12.25.32;  author jwh;  state Exp;
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56.1
date     91.11.05.10.00.57;  author jwh;  state Exp;
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55.1
date     91.08.25.10.35.48;  author jwh;  state Exp;
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54.1
date     91.03.18.15.36.32;  author jwh;  state Exp;
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50.1
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43.1
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1.2
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1.1
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desc
@HWIA_UTILS is the optimized programattic transfer routine.
It is written in assembler, and is called from
hwiProgXfer.
@


56.3
log
@
pws2rcs automatic delta on Wed Jan 27 13:14:25 MST 1993
@
text
@
	nosyms
	mname HWIA_UTILS

	src     MODULE HWIA_UTILS;
	src     import SCSI_DEFS;
	src     export
	src     procedure hwiAXfer(var XferBlock:XferBlockType; PtrScsiChip:PtrScsiChipType);
	src     END;

	def     HWIA_UTILS_HWIAXFER
	def     HWIA_UTILS_HWIA_UTILS
	def     HWIA_UTILS__BASE

regScsiChip                     equ     a4
intsOffset                      equ     9
sstsOffset                      equ     13
dataOffset                      equ     21
BitFIFOEmpty                    equ     0
BitFIFOFull                     equ     1

regXferBlock                    equ     a3
XferPhaseOffset                 equ     0
XferRetryCountOffset            equ     2
XferSavedDataPointerOffset      equ     4
XferSavedDataLengthOffset       equ     8
XferDMACountOffset              equ     12
XferBufPtrOffset                equ     16
XferBufLenOffset                equ     20
XferDoDMAOffset                 equ     24

regBufPtr                       equ     a2
regChipData                     equ     a1
regChipSsts                     equ     a0
regBufLen                       equ     d2

HWIA_UTILS__BASE              equ *
HWIA_UTILS_HWIAXFER           equ *
*******************************************************************
* set up registers
* predecrement regBufLen to compensate for dbra termination on -1.
* if the register is < 0, then 0 or negative length, do nothing in
* this case.
*******************************************************************
		move.l  8(sp),regXferBlock
		move.l  4(sp),regScsiChip
		lea     dataOffset(regScsiChip),regChipData
		lea     sstsOffset(regScsiChip),regChipSsts
		move.l  XferBufPtrOffset(regXferBlock),regBufPtr
		move.l  XferBufLenOffset(regXferBlock),regBufLen
		subq.l  #1,regBufLen
		blt.s   exit_restore

*******************************************************************
* determine if this is an inbound or outbound transfer
*******************************************************************
		cmpi.w  #1,XferPhaseOffset(regXferBlock)
		bne.w   outbound_xfer

inbound_xfer    equ     *
*******************************************************************
*  while (there is room in the buffer)
*       if fifo not empty
*               input data
*       else fifo is empty
*               wait for an interrupt or fifo not empty
*               on interrupt exit
*******************************************************************
check_fifo_empty equ    *
		btst    #BitFIFOEmpty,(regChipSsts)
		bne.s   fifo_empty
		move.b  (regChipData),(regBufPtr)+
		dbra    regBufLen,check_fifo_empty
		clr.w   regBufLen               ; dbra only works on 16 bits
		subq.l  #1,regBufLen            ; check for > 16 bit transfer
		bgt.s   check_fifo_empty
		bra.s   exit_restore
fifo_empty      equ     *
		tst.b   intsOffset(regScsiChip)
		beq.s   check_fifo_empty
		bra.s   exit_restore

outbound_xfer   equ *
*******************************************************************
*  while (there is data in the buffer)
*       if fifo not full
*               output data
*       else fifo is full
*               wait for an interrupt or fifo not full
*               on interrupt exit
*  wait for fifo to empty or an interrupt to occur
*******************************************************************
check_fifo_full equ     *
		btst    #BitFIFOFull,(regChipSsts)
		bne.s   fifo_full
		move.b  (regBufPtr)+,(regChipData)
		dbra    regBufLen,check_fifo_full
		clr.w   regBufLen               ; dbra only works on 16 bits
		subq.l  #1,regBufLen            ; check for > 16 bit transfer
		bgt.s   check_fifo_full
wait_fifo_empty equ     *
		btst    #BitFIFOEmpty,(regChipSsts)
		bne.s   exit_restore
		tst.b   intsOffset(regScsiChip)
		beq.s   wait_fifo_empty
		bra.s   exit_restore
fifo_full       equ     *
		tst.b   intsOffset(regScsiChip)
		beq.s   check_fifo_full
*               bra.s   exit_restore

exit_restore    equ *
*******************************************************************
*  restore registers into the XferBlock.  Add 1 to regBufLen
*  to get the true final count.  This compensates for dbra
*  terminating on -1.
*******************************************************************
		move.l  regBufPtr,XferBufPtrOffset(regXferBlock)
		addq.l  #1,regBufLen
		move.l  regBufLen,XferBufLenOffset(regXferBlock)

*******************************************************************
*  restore stack and go back to caller
*******************************************************************
		move.l  (sp)+,a0
		addq.w  #8,sp
		jmp     (a0)




HWIA_UTILS_HWIA_UTILS         equ *
	rts

	END
@


56.2
log
@
pws2rcs automatic delta on Wed Jan 27 11:57:27 MST 1993
@
text
@d1 135
@


56.1
log
@Automatic bump of revision number for PWS version 3.25
@
text
@a0 135

	nosyms
	mname HWIA_UTILS

	src     MODULE HWIA_UTILS;
	src     import SCSI_DEFS;
	src     export
	src     procedure hwiAXfer(var XferBlock:XferBlockType; PtrScsiChip:PtrScsiChipType);
	src     END;

	def     HWIA_UTILS_HWIAXFER
	def     HWIA_UTILS_HWIA_UTILS
	def     HWIA_UTILS__BASE

regScsiChip                     equ     a4
intsOffset                      equ     9
sstsOffset                      equ     13
dataOffset                      equ     21
BitFIFOEmpty                    equ     0
BitFIFOFull                     equ     1

regXferBlock                    equ     a3
XferPhaseOffset                 equ     0
XferRetryCountOffset            equ     2
XferSavedDataPointerOffset      equ     4
XferSavedDataLengthOffset       equ     8
XferDMACountOffset              equ     12
XferBufPtrOffset                equ     16
XferBufLenOffset                equ     20
XferDoDMAOffset                 equ     24

regBufPtr                       equ     a2
regChipData                     equ     a1
regChipSsts                     equ     a0
regBufLen                       equ     d2

HWIA_UTILS__BASE              equ *
HWIA_UTILS_HWIAXFER           equ *
*******************************************************************
* set up registers
* predecrement regBufLen to compensate for dbra termination on -1.
* if the register is < 0, then 0 or negative length, do nothing in
* this case.
*******************************************************************
		move.l  8(sp),regXferBlock
		move.l  4(sp),regScsiChip
		lea     dataOffset(regScsiChip),regChipData
		lea     sstsOffset(regScsiChip),regChipSsts
		move.l  XferBufPtrOffset(regXferBlock),regBufPtr
		move.l  XferBufLenOffset(regXferBlock),regBufLen
		subq.l  #1,regBufLen
		blt.s   exit_restore

*******************************************************************
* determine if this is an inbound or outbound transfer
*******************************************************************
		cmpi.w  #1,XferPhaseOffset(regXferBlock)
		bne.w   outbound_xfer

inbound_xfer    equ     *
*******************************************************************
*  while (there is room in the buffer)
*       if fifo not empty
*               input data
*       else fifo is empty
*               wait for an interrupt or fifo not empty
*               on interrupt exit
*******************************************************************
check_fifo_empty equ    *
		btst    #BitFIFOEmpty,(regChipSsts)
		bne.s   fifo_empty
		move.b  (regChipData),(regBufPtr)+
		dbra    regBufLen,check_fifo_empty
		clr.w   regBufLen               ; dbra only works on 16 bits
		subq.l  #1,regBufLen            ; check for > 16 bit transfer
		bgt.s   check_fifo_empty
		bra.s   exit_restore
fifo_empty      equ     *
		tst.b   intsOffset(regScsiChip)
		beq.s   check_fifo_empty
		bra.s   exit_restore

outbound_xfer   equ *
*******************************************************************
*  while (there is data in the buffer)
*       if fifo not full
*               output data
*       else fifo is full
*               wait for an interrupt or fifo not full
*               on interrupt exit
*  wait for fifo to empty or an interrupt to occur
*******************************************************************
check_fifo_full equ     *
		btst    #BitFIFOFull,(regChipSsts)
		bne.s   fifo_full
		move.b  (regBufPtr)+,(regChipData)
		dbra    regBufLen,check_fifo_full
		clr.w   regBufLen               ; dbra only works on 16 bits
		subq.l  #1,regBufLen            ; check for > 16 bit transfer
		bgt.s   check_fifo_full
wait_fifo_empty equ     *
		btst    #BitFIFOEmpty,(regChipSsts)
		bne.s   exit_restore
		tst.b   intsOffset(regScsiChip)
		beq.s   wait_fifo_empty
		bra.s   exit_restore
fifo_full       equ     *
		tst.b   intsOffset(regScsiChip)
		beq.s   check_fifo_full
*               bra.s   exit_restore

exit_restore    equ *
*******************************************************************
*  restore registers into the XferBlock.  Add 1 to regBufLen
*  to get the true final count.  This compensates for dbra
*  terminating on -1.
*******************************************************************
		move.l  regBufPtr,XferBufPtrOffset(regXferBlock)
		addq.l  #1,regBufLen
		move.l  regBufLen,XferBufLenOffset(regXferBlock)

*******************************************************************
*  restore stack and go back to caller
*******************************************************************
		move.l  (sp)+,a0
		addq.w  #8,sp
		jmp     (a0)




HWIA_UTILS_HWIA_UTILS         equ *
	rts

	END
@


55.1
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@Automatic bump of revision number for PWS version 3.25A
@
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54.1
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@Automatic bump of revision number for PWS version 3.24
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@Automatic bump of revision number for PWS version 3.24B
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@Automatic bump of revision number for PWS version 3.24A
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@Automatic bump of revision number for PWS version 3.24d
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@Automatic bump of revision number for PWS version 3.23c
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@Automatic bump of revision number for PWS version 3.24b
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@Automatic bump of revision number for PWS version 3.24a
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47.1
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@Automatic bump of revision number for PWS version 3.23
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@Automatic bump of revision number for PWS version 3.23
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@Automatic bump of revision number for PWS version 3.23C
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@Automatic bump of revision number for PWS version 3.23B
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43.1
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@Automatic bump of revision number for PWS version 3.23aA
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1.2
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@On an data out transfer, after exhausting buffer wait for FIFO to empty.
Note that is not possible to do the same for fifo in transfers.
@
text
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1.1
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@Initial revision
@
text
@d91 1
d101 5
@
