head     56.3;
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locks    ; strict;
comment  @# @;


56.3
date     93.01.27.13.58.24;  author jwh;  state Exp;
branches ;
next     56.2;

56.2
date     93.01.27.12.29.41;  author jwh;  state Exp;
branches ;
next     56.1;

56.1
date     91.11.07.12.31.31;  author jwh;  state Exp;
branches ;
next     1.1;

1.1
date     91.03.13.09.06.06;  author jwh;  state Exp;
branches ;
next     ;


desc
@@


56.3
log
@
pws2rcs automatic delta on Wed Jan 27 13:14:25 MST 1993
@
text
@*
*       x_ovfl.sa 3.1 12/10/90
*
*       fpsp_ovfl --- FPSP handler for overflow exception
*
*       Overflow occurs when a floating-point intermediate result is
*       too large to be represented in a floating-point data register,
*       or when storing to memory, the contents of a floating-point
*       data register are too large to be represented in the
*       destination format.
*
* Trap disabled results
*
* If the instruction is move_out, then garbage is stored in the
* destination.  If the instruction is not move_out, then the
* destination is not affected.  For 68881 compatibility, the
* following values should be stored at the destination, based
* on the current rounding mode:
*
*  RN   Infinity with the sign of the intermediate result.
*  RZ   Largest magnitude number, with the sign of the
*       intermediate result.
*  RM   For pos overflow, the largest pos number. For neg overflow,
*       -infinity
*  RP   For pos overflow, +infinity. For neg overflow, the largest
*       neg number
*
* Trap enabled results
* All trap disabled code applies.  In addition the exceptional
* operand needs to be made available to the users exception handler
* with a bias of $6000 subtracted from the exponent.
*
*

*               Copyright (C) Motorola, Inc. 1990
*                       All Rights Reserved
*
*       THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
*       The copyright notice above does not evidence any
*       actual or intended publication of such source code.



	include fpsp_h

	refr    ovf_r_x2
	refr    ovf_r_x3
	refr    store
	refr    real_ovfl
	refr    real_inex
	refr    fpsp_done
	refr    g_opcls
	refr    b1238_fix

	def     fpsp_ovfl
fpsp_ovfl    equ    *
	link            a6,#-LOCAL_SIZE
	fsave           -(a7)
	movem.l         d0-d1/a0-a1,USER_DA(a6)
	fmovem.x        fp0-fp3,USER_FP0(a6)
	fmovem.l        FPCONTROL/FPSTATUS/FPIADDR,USER_FPCONTROL(a6)
*
*       The 040 doesn't set the AINEX bit in the FPSTATUS, the following
*       line temporarily rectifies this error.
*
	bset    #ainex_bit,FPSTATUS_AEXCEPT(a6)
*
	bsr.l   ovf_adj         ;denormalize, round & store interm op
*
*       if overflow traps not enabled check for inexact exception
*
	btst    #ovfl_bit,FPCONTROL_ENABLE(a6)
	beq.b   ck_inex
*
	btst            #E3,E_BYTE(a6)
	beq.b           no_e3_1
	bfextu          CMDREG1B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
no_e3_1    equ    *
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           real_ovfl
*
* It is possible to have either inex2 or inex1 exceptions with the
* ovfl.  If the inex enable bit is set in the FPCONTROL, and either
* inex2 or inex1 occured, we must clean up and branch to the
* real inex handler.
*
ck_inex    equ    *
	move.b          FPCONTROL_ENABLE(a6),d0
	and.b           FPSTATUS_EXCEPT(a6),d0
	andi.b          #$3,d0
	beq.b           ovfl_exit
*
* Inexact enabled and reported, and we must take an inexact exception.
*
take_inex    equ    *
	btst            #E3,E_BYTE(a6)
	beq.b           no_e3_2
	bfextu          CMDREG1B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
no_e3_2    equ    *
	move.b          #INEX_VEC,EXC_VEC+1(a6)
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           real_inex

ovfl_exit    equ    *
	bclr    #E3,E_BYTE(a6)  ;test and clear E3 bit
	beq.b   e1_set
*
* Clear dirty bit on dest resister in the frame before branching
* to b1238_fix.
*
	bfextu          CMDREG1B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix               ;test for bug1238 case

	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           fpsp_done
e1_set    equ    *
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	unlk            a6
	bra.l           fpsp_done

*
*       ovf_adj
*
ovf_adj    equ    *
*
* Have a0 point to the correct operand.
*
	btst    #E3,E_BYTE(a6)  ;test E3 bit
	beq.b   ovf_e1

	lea     WBTEMP(a6),a0
	bra.b   ovf_com
ovf_e1    equ    *
	lea     ETEMP(a6),a0

ovf_com    equ    *
	bclr    #sign_bit,LOCAL_EX(a0)
	sne     LOCAL_SGN(a0)

	bsr.l   g_opcls         ;returns opclass in d0
	cmpi.w  #3,d0           ;check for opclass3
	bne.b   not_opc011

*
* FPSTATUS_CC is saved and restored because ovf_r_x3 affects it. The
* CCs are defined to be 'not affected' for the opclass3 instruction.
*
	move.b  FPSTATUS_CC(a6),L_SCR1(a6)
	bsr.l   ovf_r_x3        ;returns a0 pointing to result
	move.b  L_SCR1(a6),FPSTATUS_CC(a6)
	bra.l   store           ;stores to memory or register

not_opc011    equ    *
	bsr.l   ovf_r_x2        ;returns a0 pointing to result
	bra.l   store           ;stores to memory or register

	end
@


56.2
log
@
pws2rcs automatic delta on Wed Jan 27 11:57:27 MST 1993
@
text
@d1 182
@


56.1
log
@Automatic bump of revision number for PWS version 3.25
@
text
@a0 182
*
*       x_ovfl.sa 3.1 12/10/90
*
*       fpsp_ovfl --- FPSP handler for overflow exception
*
*       Overflow occurs when a floating-point intermediate result is
*       too large to be represented in a floating-point data register,
*       or when storing to memory, the contents of a floating-point
*       data register are too large to be represented in the
*       destination format.
*
* Trap disabled results
*
* If the instruction is move_out, then garbage is stored in the
* destination.  If the instruction is not move_out, then the
* destination is not affected.  For 68881 compatibility, the
* following values should be stored at the destination, based
* on the current rounding mode:
*
*  RN   Infinity with the sign of the intermediate result.
*  RZ   Largest magnitude number, with the sign of the
*       intermediate result.
*  RM   For pos overflow, the largest pos number. For neg overflow,
*       -infinity
*  RP   For pos overflow, +infinity. For neg overflow, the largest
*       neg number
*
* Trap enabled results
* All trap disabled code applies.  In addition the exceptional
* operand needs to be made available to the users exception handler
* with a bias of $6000 subtracted from the exponent.
*
*

*               Copyright (C) Motorola, Inc. 1990
*                       All Rights Reserved
*
*       THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
*       The copyright notice above does not evidence any
*       actual or intended publication of such source code.



	include fpsp_h

	refr    ovf_r_x2
	refr    ovf_r_x3
	refr    store
	refr    real_ovfl
	refr    real_inex
	refr    fpsp_done
	refr    g_opcls
	refr    b1238_fix

	def     fpsp_ovfl
fpsp_ovfl    equ    *
	link            a6,#-LOCAL_SIZE
	fsave           -(a7)
	movem.l         d0-d1/a0-a1,USER_DA(a6)
	fmovem.x        fp0-fp3,USER_FP0(a6)
	fmovem.l        FPCONTROL/FPSTATUS/FPIADDR,USER_FPCONTROL(a6)
*
*       The 040 doesn't set the AINEX bit in the FPSTATUS, the following
*       line temporarily rectifies this error.
*
	bset    #ainex_bit,FPSTATUS_AEXCEPT(a6)
*
	bsr.l   ovf_adj         ;denormalize, round & store interm op
*
*       if overflow traps not enabled check for inexact exception
*
	btst    #ovfl_bit,FPCONTROL_ENABLE(a6)
	beq.b   ck_inex
*
	btst            #E3,E_BYTE(a6)
	beq.b           no_e3_1
	bfextu          CMDREG1B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
no_e3_1    equ    *
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           real_ovfl
*
* It is possible to have either inex2 or inex1 exceptions with the
* ovfl.  If the inex enable bit is set in the FPCONTROL, and either
* inex2 or inex1 occured, we must clean up and branch to the
* real inex handler.
*
ck_inex    equ    *
	move.b          FPCONTROL_ENABLE(a6),d0
	and.b           FPSTATUS_EXCEPT(a6),d0
	andi.b          #$3,d0
	beq.b           ovfl_exit
*
* Inexact enabled and reported, and we must take an inexact exception.
*
take_inex    equ    *
	btst            #E3,E_BYTE(a6)
	beq.b           no_e3_2
	bfextu          CMDREG1B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix
	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
no_e3_2    equ    *
	move.b          #INEX_VEC,EXC_VEC+1(a6)
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           real_inex

ovfl_exit    equ    *
	bclr    #E3,E_BYTE(a6)  ;test and clear E3 bit
	beq.b   e1_set
*
* Clear dirty bit on dest resister in the frame before branching
* to b1238_fix.
*
	bfextu          CMDREG1B(a6){6:3},d0    ;get dest reg no
	bclr            d0,FPR_DIRTY_BITS(a6)   ;clr dest dirty bit
	bsr.l           b1238_fix               ;test for bug1238 case

	move.l          USER_FPSTATUS(a6),FPSTATUS_SHADOW(a6)
	ori.l           #sx_mask,E_BYTE(a6)
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	frestore        (a7)+
	unlk            a6
	bra.l           fpsp_done
e1_set    equ    *
	movem.l         USER_DA(a6),d0-d1/a0-a1
	fmovem.x        USER_FP0(a6),fp0-fp3
	fmovem.l        USER_FPCONTROL(a6),FPCONTROL/FPSTATUS/FPIADDR
	unlk            a6
	bra.l           fpsp_done

*
*       ovf_adj
*
ovf_adj    equ    *
*
* Have a0 point to the correct operand.
*
	btst    #E3,E_BYTE(a6)  ;test E3 bit
	beq.b   ovf_e1

	lea     WBTEMP(a6),a0
	bra.b   ovf_com
ovf_e1    equ    *
	lea     ETEMP(a6),a0

ovf_com    equ    *
	bclr    #sign_bit,LOCAL_EX(a0)
	sne     LOCAL_SGN(a0)

	bsr.l   g_opcls         ;returns opclass in d0
	cmpi.w  #3,d0           ;check for opclass3
	bne.b   not_opc011

*
* FPSTATUS_CC is saved and restored because ovf_r_x3 affects it. The
* CCs are defined to be 'not affected' for the opclass3 instruction.
*
	move.b  FPSTATUS_CC(a6),L_SCR1(a6)
	bsr.l   ovf_r_x3        ;returns a0 pointing to result
	move.b  L_SCR1(a6),FPSTATUS_CC(a6)
	bra.l   store           ;stores to memory or register

not_opc011    equ    *
	bsr.l   ovf_r_x2        ;returns a0 pointing to result
	bra.l   store           ;stores to memory or register

	end
@


1.1
log
@Initial revision
@
text
@@
