head     56.3;
access   ;
symbols  ;
locks    ; strict;
comment  @# @;


56.3
date     93.01.27.13.58.17;  author jwh;  state Exp;
branches ;
next     56.2;

56.2
date     93.01.27.12.29.34;  author jwh;  state Exp;
branches ;
next     56.1;

56.1
date     91.11.07.12.31.23;  author jwh;  state Exp;
branches ;
next     1.1;

1.1
date     91.03.13.09.05.05;  author jwh;  state Exp;
branches ;
next     ;


desc
@@


56.3
log
@
pws2rcs automatic delta on Wed Jan 27 13:14:25 MST 1993
@
text
@*
*       Program Name: x_inex.sa 1.10 7/10/90
*
*       Description:  inexact result
*              inex1 & inex2 share trap vector# 49.
*
*       Input:
*       Configuration L - inex2
*       Destination (memory or FP-reg) always contains correct result - no fixup
*         required by supervisor trap handler.
*       Opclass: 0xx
*       Rx:      don't care
*       E1 exception, integer stack = 4-word (pre) or 6-word (post)
*       E3 exception, integer stack = 4-word (pre) or 6-word (post)
*
*       For E1 exceptions - short fsave stack
*
*            ------------------------------------------------------------------
* a7->28     | version# = $40 | byte count = $28 |$0000
*            ------------------------------------------------------------------
*     24     |STAG {31:29)
*            ------------------------------------------------------------------
*     20     |CMDREG1B - opclass{31:29} rx{12:10} ry{9:7} extension{6:0}
*            ------------------------------------------------------------------
*     1c     |DTAG {31:29}
*            ------------------------------------------------------------------
*     18     |E1{26}, E3{25}
*            ------------------------------------------------------------------
*     14     |FPTS - dest sign|FPTE - destination op (ry) exponent | 0000
*            ------------------------------------------------------------------
*     10     |FPTM{63:32} - destination op mantissa (msl)
*            ------------------------------------------------------------------
*      c     |FPTM{31:00} - destination op mantissa (lsl)
*            ------------------------------------------------------------------
*      8     |ETS - source sign|ETE - source op (rx) exponent | 0000
*            ------------------------------------------------------------------
*      4     |ETM{63:32} - source op mantissa (msl)
*            ------------------------------------------------------------------
* a6-> 0     |ETM{31:00} - source op mantissa (lsl)
*            ------------------------------------------------------------------
*                                         15                                  0
*                                         -------------------------------------
*      4                                  | status register
*                                         -------------------------------------
*      6                                  | program counter (msw)
*                                         -------------------------------------
*      8                                  | program counter (lsw)
*                                         -------------------------------------
*      a                                  | format#/vector offset
*                                         -------------------------------------
*
*
*       For E3 exceptions - busy fsave stack
*            ------------------------------------------------------------------
* a7->60     | version# = $40 | byte count = $60         |$0000
*            ------------------------------------------------------------------
*     5c     | TTE
*            ------------------------------------------------------------------
*     58     | CU SAVEPC
*            ------------------------------------------------------------------
*     54     | YTE
*            ------------------------------------------------------------------
*     50     | STM
*            ------------------------------------------------------------------
*     4c     | STM
*            ------------------------------------------------------------------
*     48     | WBTE
*            ------------------------------------------------------------------
*     44     | WBTM
*            ------------------------------------------------------------------
*     40     | WBTM
*            ------------------------------------------------------------------
*     3c     | STAT
*            ------------------------------------------------------------------
*     38     | FPIARCU
*            ------------------------------------------------------------------
*     34     | FPIARXU
*            ------------------------------------------------------------------
*     30     | CMDREG 2B
*            ------------------------------------------------------------------
*     2c     | CMDREG 3B
*            ------------------------------------------------------------------
*     28     | NMNEXC
*            ------------------------------------------------------------------
*     24     |STAG {31:29)
*            ------------------------------------------------------------------
*     20     |CMDREG1B - opclass{31:29} rx{12:10} ry{9:7} extension{6:0}
*            ------------------------------------------------------------------
*     1c     |DTAG {31:29}
*            ------------------------------------------------------------------
*     18     |E1{26}, E3{25}
*            ------------------------------------------------------------------
*     14     |FPTS - dest sign|FPTE - destination op (ry) exponent | 0000
*            ------------------------------------------------------------------
*     10     |FPTM{63:32} - destination op mantissa (msl)
*            ------------------------------------------------------------------
*      c     |FPTM{31:00} - destination op mantissa (lsl)
*            ------------------------------------------------------------------
*      8     |ETS - source sign|ETE - source op (rx) exponent | 0000
*            ------------------------------------------------------------------
*      4     |ETM{63:32} - source op mantissa (msl)
*            ------------------------------------------------------------------
* a6-> 0     |ETM{31:00} - source op mantissa (lsl)
*            ------------------------------------------------------------------
*                                         15                                  0
*                                         -------------------------------------
*      4                                  | status register
*                                         -------------------------------------
*      6                                  | program counter (msw)
*                                         -------------------------------------
*      8                                  | program counter (lsw)
*                                         -------------------------------------
*      c                                  | format#/vector offset
*                                         -------------------------------------
*
*
*
*Output:
*       Inex2 - Trap enabled:
*               The rounded result is delivered to the destination by the 040,
*               no 'supervisor' code is needed.  Note that the exceptional
*               operand is undefined.
*
*       Inex1 - Trap enabled:
*               E3 is cleared in the fsave stack.  The fsave stack is then
*               restored.
*
*Modifies:
*       No registers are modified.
*
*Speed:
*
*Object Size
*
*External References
*       user - the users exception handler.
*
*Algorithm
*
*       begin
*               fsave
*               call user handler (exceptional operand is not defined)
*                  if inex1
*                       if (E3=1)
*                         clear E3 bit in fsave stack
*                         frestore
*                         adjust sp to skip down to return addr in integer stack
*                         rte
*
*                       else (E1=1)
*                         adjust sp to skip down to return addr in integer stack
*                         rte
*                  else inex2
*                         clear E1 bit in fsave stack
*                         frestore
*                         adjust sp to skip down to return addr in integer stack
*                         rte
*       end
*
*Implementation Notes
*
*
*  Notes:
*       The fix for errata #9 (Rev 1.5 July 6, 1990 68040 errata)
*       is included.
*



INEX1   equ     8
INEX2   equ     9
E3      equ     2
E1      equ     1
TFLAG   equ     4
E_BYTE  equ     $18
T_BYTE  equ     $19
VERN    equ     $40
INTPC   equ     6



	refr    usr_in_t

	def    inex_hd
inex_hd    equ    *
	fsave   -(a7)

	link    a6,#0           ;push a6, a6 -> top of stack, a7 -> top of stack
	adda.w  #4,a6           ;a6 -> top of fsave
	move.b  #0,(a6)         ;clear ver# so can use word for fsave stack size
	adda.w  (a6),a6         ;add stack size - a6 points to bottom of fsave
*
*At this point:
*a7 -> top of stack (saved contents of a6)
*a6 -> bottom of fsave stack
*
*** Fix for errata #9 (Rev 1.5 July 6, 1990 68040 errata) ***
	move.l  d0,-(a7)                ;use d0 for scratch
	fmove.l FPIADDR,d0                ;get FPIAR
	cmp.l   INTPC(a6),d0            ;compare to int pc, if match, and TFLAG
	bne.b   not_err         ;clear, we have the bug condition
	btst  #TFLAG,-T_BYTE(a6)      ;test TFLAG
	beq.b   not_err         ;if set, clear E1 and restore
	bclr  #E1,-E_BYTE(a6)         ;do the clear
	move.l  (a7)+,d0                ;return the scratch
	frestore (a7)+                  ;restore and handle the pre-exc
	bra.b   exit
not_err    equ    *
	move.l  (a7)+,d0    ;restore d0
*** End of errata #9 fix ***

real_inx    equ    *
	jsr   usr_in_t                ;call the users handler

	bclr  #E3,-E_BYTE(a6)         ;clear and test E3 flag
	beq.b   ck_e1                   ;if not set, it is E1
	bra.b   rst_out                 ;do restore
ck_e1    equ    *
	bclr  #E1,-E_BYTE(a6)         ;clear E1 flag
rst_out    equ    *
	move.l  (a7)+,a6        ;restore a6 from link
	addi.b   #VERN,(a7)      ;replace version number
	frestore (a7)+

exit    equ    *
	rte
	end
@


56.2
log
@
pws2rcs automatic delta on Wed Jan 27 11:57:27 MST 1993
@
text
@d1 227
@


56.1
log
@Automatic bump of revision number for PWS version 3.25
@
text
@a0 227
*
*       Program Name: x_inex.sa 1.10 7/10/90
*
*       Description:  inexact result
*              inex1 & inex2 share trap vector# 49.
*
*       Input:
*       Configuration L - inex2
*       Destination (memory or FP-reg) always contains correct result - no fixup
*         required by supervisor trap handler.
*       Opclass: 0xx
*       Rx:      don't care
*       E1 exception, integer stack = 4-word (pre) or 6-word (post)
*       E3 exception, integer stack = 4-word (pre) or 6-word (post)
*
*       For E1 exceptions - short fsave stack
*
*            ------------------------------------------------------------------
* a7->28     | version# = $40 | byte count = $28 |$0000
*            ------------------------------------------------------------------
*     24     |STAG {31:29)
*            ------------------------------------------------------------------
*     20     |CMDREG1B - opclass{31:29} rx{12:10} ry{9:7} extension{6:0}
*            ------------------------------------------------------------------
*     1c     |DTAG {31:29}
*            ------------------------------------------------------------------
*     18     |E1{26}, E3{25}
*            ------------------------------------------------------------------
*     14     |FPTS - dest sign|FPTE - destination op (ry) exponent | 0000
*            ------------------------------------------------------------------
*     10     |FPTM{63:32} - destination op mantissa (msl)
*            ------------------------------------------------------------------
*      c     |FPTM{31:00} - destination op mantissa (lsl)
*            ------------------------------------------------------------------
*      8     |ETS - source sign|ETE - source op (rx) exponent | 0000
*            ------------------------------------------------------------------
*      4     |ETM{63:32} - source op mantissa (msl)
*            ------------------------------------------------------------------
* a6-> 0     |ETM{31:00} - source op mantissa (lsl)
*            ------------------------------------------------------------------
*                                         15                                  0
*                                         -------------------------------------
*      4                                  | status register
*                                         -------------------------------------
*      6                                  | program counter (msw)
*                                         -------------------------------------
*      8                                  | program counter (lsw)
*                                         -------------------------------------
*      a                                  | format#/vector offset
*                                         -------------------------------------
*
*
*       For E3 exceptions - busy fsave stack
*            ------------------------------------------------------------------
* a7->60     | version# = $40 | byte count = $60         |$0000
*            ------------------------------------------------------------------
*     5c     | TTE
*            ------------------------------------------------------------------
*     58     | CU SAVEPC
*            ------------------------------------------------------------------
*     54     | YTE
*            ------------------------------------------------------------------
*     50     | STM
*            ------------------------------------------------------------------
*     4c     | STM
*            ------------------------------------------------------------------
*     48     | WBTE
*            ------------------------------------------------------------------
*     44     | WBTM
*            ------------------------------------------------------------------
*     40     | WBTM
*            ------------------------------------------------------------------
*     3c     | STAT
*            ------------------------------------------------------------------
*     38     | FPIARCU
*            ------------------------------------------------------------------
*     34     | FPIARXU
*            ------------------------------------------------------------------
*     30     | CMDREG 2B
*            ------------------------------------------------------------------
*     2c     | CMDREG 3B
*            ------------------------------------------------------------------
*     28     | NMNEXC
*            ------------------------------------------------------------------
*     24     |STAG {31:29)
*            ------------------------------------------------------------------
*     20     |CMDREG1B - opclass{31:29} rx{12:10} ry{9:7} extension{6:0}
*            ------------------------------------------------------------------
*     1c     |DTAG {31:29}
*            ------------------------------------------------------------------
*     18     |E1{26}, E3{25}
*            ------------------------------------------------------------------
*     14     |FPTS - dest sign|FPTE - destination op (ry) exponent | 0000
*            ------------------------------------------------------------------
*     10     |FPTM{63:32} - destination op mantissa (msl)
*            ------------------------------------------------------------------
*      c     |FPTM{31:00} - destination op mantissa (lsl)
*            ------------------------------------------------------------------
*      8     |ETS - source sign|ETE - source op (rx) exponent | 0000
*            ------------------------------------------------------------------
*      4     |ETM{63:32} - source op mantissa (msl)
*            ------------------------------------------------------------------
* a6-> 0     |ETM{31:00} - source op mantissa (lsl)
*            ------------------------------------------------------------------
*                                         15                                  0
*                                         -------------------------------------
*      4                                  | status register
*                                         -------------------------------------
*      6                                  | program counter (msw)
*                                         -------------------------------------
*      8                                  | program counter (lsw)
*                                         -------------------------------------
*      c                                  | format#/vector offset
*                                         -------------------------------------
*
*
*
*Output:
*       Inex2 - Trap enabled:
*               The rounded result is delivered to the destination by the 040,
*               no 'supervisor' code is needed.  Note that the exceptional
*               operand is undefined.
*
*       Inex1 - Trap enabled:
*               E3 is cleared in the fsave stack.  The fsave stack is then
*               restored.
*
*Modifies:
*       No registers are modified.
*
*Speed:
*
*Object Size
*
*External References
*       user - the users exception handler.
*
*Algorithm
*
*       begin
*               fsave
*               call user handler (exceptional operand is not defined)
*                  if inex1
*                       if (E3=1)
*                         clear E3 bit in fsave stack
*                         frestore
*                         adjust sp to skip down to return addr in integer stack
*                         rte
*
*                       else (E1=1)
*                         adjust sp to skip down to return addr in integer stack
*                         rte
*                  else inex2
*                         clear E1 bit in fsave stack
*                         frestore
*                         adjust sp to skip down to return addr in integer stack
*                         rte
*       end
*
*Implementation Notes
*
*
*  Notes:
*       The fix for errata #9 (Rev 1.5 July 6, 1990 68040 errata)
*       is included.
*



INEX1   equ     8
INEX2   equ     9
E3      equ     2
E1      equ     1
TFLAG   equ     4
E_BYTE  equ     $18
T_BYTE  equ     $19
VERN    equ     $40
INTPC   equ     6



	refr    usr_in_t

	def    inex_hd
inex_hd    equ    *
	fsave   -(a7)

	link    a6,#0           ;push a6, a6 -> top of stack, a7 -> top of stack
	adda.w  #4,a6           ;a6 -> top of fsave
	move.b  #0,(a6)         ;clear ver# so can use word for fsave stack size
	adda.w  (a6),a6         ;add stack size - a6 points to bottom of fsave
*
*At this point:
*a7 -> top of stack (saved contents of a6)
*a6 -> bottom of fsave stack
*
*** Fix for errata #9 (Rev 1.5 July 6, 1990 68040 errata) ***
	move.l  d0,-(a7)                ;use d0 for scratch
	fmove.l FPIADDR,d0                ;get FPIAR
	cmp.l   INTPC(a6),d0            ;compare to int pc, if match, and TFLAG
	bne.b   not_err         ;clear, we have the bug condition
	btst  #TFLAG,-T_BYTE(a6)      ;test TFLAG
	beq.b   not_err         ;if set, clear E1 and restore
	bclr  #E1,-E_BYTE(a6)         ;do the clear
	move.l  (a7)+,d0                ;return the scratch
	frestore (a7)+                  ;restore and handle the pre-exc
	bra.b   exit
not_err    equ    *
	move.l  (a7)+,d0    ;restore d0
*** End of errata #9 fix ***

real_inx    equ    *
	jsr   usr_in_t                ;call the users handler

	bclr  #E3,-E_BYTE(a6)         ;clear and test E3 flag
	beq.b   ck_e1                   ;if not set, it is E1
	bra.b   rst_out                 ;do restore
ck_e1    equ    *
	bclr  #E1,-E_BYTE(a6)         ;clear E1 flag
rst_out    equ    *
	move.l  (a7)+,a6        ;restore a6 from link
	addi.b   #VERN,(a7)      ;replace version number
	frestore (a7)+

exit    equ    *
	rte
	end
@


1.1
log
@Initial revision
@
text
@@
