From zac@hpislzac Wed Aug 15 11:56 MDT 1990
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Date: Wed, 15 Aug 90 11:52:48 mdt
From: Steve Elbinger <zac@hpislzac>
Full-Name: Steve Elbinger
Message-Id: <9008151752.AA06394@hpislzac.lvld.hp.com>
To: jwh@hpfclw
Subject: Cache info from Dave Dahms
Status: RO



Dave says it's ok to flush the cache during a bus error recovery
on the 68040.


        Where does the writeback data come from?  WB[1,2,3]D?
        
        - inside the pipeline operation, if there is a memory read 
          and write in the same cycle, the write will get buffered.  
          Up to three writes can get buffered.  If one of the reads
          bus errors, the write data get's placed on the stack
          in WB[1,2,3]D.

zac

