			   HOW TO USE RUG
		        Updated Aug 12, 1987
			FOR INTERNAL HP USE ONLY



			    ADDRESS MAP

Note: All addresses are chip offsets.
      All addresses are in hex.

Name        Address(es)        Type
-----------------------------------------------------------------------------
BUSY        044                Read Only (reads BUSY on D8-D15)

INTB        04C                (dummy for compatibility - generates IMA)
 
INTENB      098                (dummy for compatibility - generates IMA)

TRIGGER     09C                R/W (reads BUSY on D8-D15)

CURSOR
DUMMY 1     0AC                (dummy for compatibility - generates IMA)

CURSOR
DUMMY 2     10A                (dummy for compatibility - generates IMA)

CURSOR
DUMMY 3     10E                (dummy for compatibility - generates IMA)

CURSOR
DUMMY 4     112                (dummy for compatibility - generates IMA)

XSRC        0F2                R/W
            210
            310                (causes trigger)

YSRC        0F6                R/W
            212
            312                (causes trigger)

XDST        0FA                R/W
            214
            314                (causes trigger)

YDST        0FE                R/W
            216
            316                (causes trigger)

FX          102                R/W
            208
            308                (causes trigger)

FY          106                R/W
            20A
            30A                (causes trigger)

XS/XD       200                Write Only
            300                (causes trigger)
 
NO-OP       202                Read Only (Revision/ID)
            302                (causes trigger)

CONTROL/ID  204                R/W
            304                (causes trigger)

COMMAND/    206                R/W
STATUS      306                (causes trigger)

LINETYPE    20C                R/W
            30C                (causes trigger)

LTP         20E                R/W
            30E                (causes trigger)

XMIN        218                R/W
            318                (causes trigger)

XMAX        21A                R/W
            31A                (causes trigger)

YMIN        21C                R/W
            31C                (causes trigger)

YMAX        21E                R/W
            31E                (causes trigger)







			REGISTER DEFINITIONS

The BUSY register (offset 0x044):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 |BSY|BSY|BSY|BSY|BSY|BSY|BSY|BSY| - | - | - | - | - | - | - | - |
	 -----------------------------------------------------------------

	 This register is for compatiblity with the TOPCAT block mover chip.
	 Reading this register returns 1 in the upper eight bits when RUG is 
	 busy, 0 otherwise.  New software should not use this register for 
	 checking the status of RUG.



The INTB register (offset 0x04C):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
	 -----------------------------------------------------------------

	 This register is a dummy register for compatibility with the
	 TOPCAT block mover chip.  Reading or writing has no effect other
	 than to assert IMA.



The INTENB register (offset 0x098):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
	 -----------------------------------------------------------------

	 This register is a dummy register for compatibility with the
	 TOPCAT block mover chip.  Reading or writing has no effect other
	 than to assert IMA.



The TRIGGER register (offset 0x09c):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 |BSY|BSY|BSY|BSY|BSY|BSY|BSY|BSY| - | - | - | - | - | - | - | - |
	 -----------------------------------------------------------------

	 This register is for compatibility with the TOPCAT block mover
	 chip.  Writing any data to this register will trigger an operation
	 in RUG.  Reading from this register will read BUSY on bits 8-15.



The CURSOR DUMMY registers (offsets 0x0ac, 0x10a, 0x10e, 0x112):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
	 -----------------------------------------------------------------

	 These registers are dummy registers for compatibility with the
	 TOPCAT block mover chip.  Reading or writing has no effect other
	 than to assert IMA.



The XS/XD register (offset 0x200):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |X11|X10|X9 |X8 |X7 |X6 |X5 |X4 |X3 |X2 |X1 |X0 |
	 -----------------------------------------------------------------

	Writing to this register will cause data to be written to both
	the XSRC and XDST registers at the same time.  The XS/XD register
	is meant to be used for the circle primitive since both the XSRC
	and XDST registers need to be loaded with the X center coordinate
	for filled circles.



The NO-OP register (offset 0x202):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 |REV|REV|REV|REV|REV|REV|REV|REV| - | - | - | - | - | - | - | - |
	 -----------------------------------------------------------------

	This register is a dummy register for compatibility with the TOPCAT
	block mover chip.  Reading will return the revision number in 
	bits 8-15.



The CONTROL/ID Register (offset 0x204):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 |REV|REV|REV|REV|REV|REV|REV|REV|CLP| - |PM |RLD|SL3|SL2|SL1|SL0|
	 -----------------------------------------------------------------

	Bit 0-3: SCAN LINES (R/W) - Number of scan lines per page in VRAM

		3 2 1 0     Number of scan lines per page
		-----------------------------------------
		0 0 0 0     16
		1 0 0 0     8
		1 1 0 0     4
		1 1 1 0     2
		1 1 1 1     1

		All other values are illegal and will cause incorrect
		operation.

	Bit 4: AUTO RELOAD (R/W) - set to 1 to enable the Auto Reload
	       feature for operation with the serial port.  Set to 0
	       to disable the Auto Reload feature.  Auto Reload allows
	       the device controlling the serial port to cause RUG to
	       reset the Linetype to the beginning of the pattern.

	Bit 5: PAGE MODE (R/W) - set to 1 to enable page mode operation,
	       set to 0 to disable page mode operation.

	Bit 6: not defined.

	Bit 7: CLIPPING ENABLE (R/W) - set to 1 to enable pixel clipping,
	       set to 0 to disable pixel clipping.

	Bit 8-15: RUG REVISION (R) - Chip revision number.



The COMMAND/STATUS register (offset 0x206):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - | - | - |RFD|BSY|OS1|OS0|VB |ENF|PCK|REP|INP| - |
	 -----------------------------------------------------------------

	Bit 0: not defined

	Bit 1: INPUT SEL (R/W) - set to 0 to use the processor port to set up 
	       and trigger the chip, set to 1 to use the serial port to set up 
	       and trigger the chip.

	Bit 2: VERT REP (R/W) - set to 0 to disable vertical replication during 
	       blits, set to 1 to enable vertical replication during blits.

	Bit 3: PICK (R/W) - RUG will set this bit if pixels were generated
	       (not clipped) during the last primitive.  The bit may be
	       set or cleared through a processor write.  It affects the
	       external PICK signal.

	Bit 4: ENABLE FB (R/W) - set to 0 to disable external cycle requests
	       by RUG, set to 1 to enable external cycle requests.  When set
	       to 0, RUG will generate all unclipped pixels internally but will
	       not issue any bus requests. 

	Bit 5: CIRCLE/VECTOR (R/W) - set to 0 to enable vector mode, set to
	       1 to enable circle mode.

	Bit 6, 7: OPERATION SELECT (R/W)

		7  6     Operation
		------------------------------------------------------------
		0  0     Solid linetype vector or circle
		0  1     Linetype vector or circle
		1  0     Bit Blit mode (bit 5 is don't care)
		1  1     Fill mode (filled circles if bit 5 is set to 1)

	Bit 8: BUSY (R) - RUG will set this bit while it is drawing a
	       primitive and will clear the bit while quiescent.  This is the
	       same as the external BUSY signal.

	Bit 9: RUG RFD (R) - RUG will clear this bit while it is ready for
	       data and set it when it cannot accept data in the XSRC,
	       YSRC, XDST and YDST registers.  Bit 9 is the same as the
	       external RFD signal and is used primarily as a handshaking
	       signal with the hardware connected to the serial inputs.

	Bit 10 - 15: not defined.



The FX Register (offset 0x208):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |X11|X10|X9 |X8 |X7 |X6 |X5 |X4 |X3 |X2 |X1 |X0 |
	 -----------------------------------------------------------------

	Multipurpose register used as shown for the following operations:

	    Vectors: Not used

	    Circles: Not used

	    Blits: Holds the width, in pixels, of the region to blit.

	    Polygon fill: Holds the X anchor coordinate.



The FY Register (offset 0x20a):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |Y11|Y10|Y9 |Y8 |Y7 |Y6 |Y5 |Y4 |Y3 |Y2 |Y1 |Y0 |
	 -----------------------------------------------------------------

	Multipurpose register used as shown for the following operations:

	    Vectors: Not used

	    Circles: Holds the radius, in pixels, of the circle.

	    Blits: Holds the height, in pixels, of the region to blit.

	    Polygon fill: Holds the Y anchor coordinate.



The LINETYPE Register (offset 0x20c):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 |L15|L14|L13|L12|L11|L10|L9 |L8 |L7 |L6 |L5 |L4 |L3 |L2 |L1 |L0 |
	 -----------------------------------------------------------------

	The LINETYPE register holds the 16 bit pattern used in generating
	linetype vectors and circles.  The LINETYPE register is scanned from
	least significant bit (0) to most significant bit (15).  Pixels will
	be generated for each position in the LINETYPE register that is set
	to 1.



The LTP Register (offset 0x20e):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |EF3|EF2|EF1|EF0|RC3|RC2|RC1|RC0|PP3|PP2|PP1|PP0|
	 -----------------------------------------------------------------

	The LTP (LineType Pointer) register controls the magnification
	factor and starting position in the LINETYPE register.  It consists
	of three fields:

	    Expansion Factor field (bits 11-8): The Expansion Factor controls
	    the number of pixel positions that each bit position in the 
	    LINETYPE register affects. Assuming that mag factor (0-15) is the
	    expansion factor desired, the Expansion Factor is computed as 
	    follows

		Expansion Factor = 0xf - mag factor.

	    Replicaton Counter field (bits 7-4): The Replication Counter is
	    used to count pixel positions for each bit in the LINETYPE
	    register.  This counter counts up until it becomes equal to 0xf, 
	    then increments the Pixel Pointer field and reloads itself with
	    the contents of the Expansion Factor field.  It initially must be
	    loaded manually, usually with the same contents as the Expansion 
	    Factor, to insure proper intialization of the linetype.

	    Pixel Pointer field (bits 3-0): The Pixel Pointer is used as an
	    index into the LINETYPE register to indicate which bit position
	    to use in controlling pixel generation.  When initializing the
	    linetype, the Pixel Pointer field should be loaded with 0 in order
	    to start at the correct bit position in the LINETYPE register.


The XSRC Register (offset 0x210):
	
	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |X11|X10|X9 |X8 |X7 |X6 |X5 |X4 |X3 |X2 |X1 |X0 |
	 -----------------------------------------------------------------

	Multipurpose register used as shown for the following operations:

	    Vectors: Holds X starting coordinate.

	    Circles: Holds X center coordinate.

	    Blits: Holds X coordinate for source rectangle.

	    Polygon fill: Holds X coordinate of a triangle.



The YSRC Register (offset 0x212):
	
	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |Y11|Y10|Y9 |Y8 |Y7 |Y6 |Y5 |Y4 |Y3 |Y2 |Y1 |Y0 |
	 -----------------------------------------------------------------

	Multipurpose register used as shown for the following operations:

	    Vectors: Holds Y starting coordinate.

	    Circles: Holds Y center coordinate.

	    Blits: Holds Y coordinate for source rectangle.

	    Polygon fill: Holds Y coordinate of a triangle.



The XDST Register (offset 0x214):
	
	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |X11|X10|X9 |X8 |X7 |X6 |X5 |X4 |X3 |X2 |X1 |X0 |
	 -----------------------------------------------------------------

	Multipurpose register used as shown for the following operations:

	    Vectors: Holds X stopping coordinate.

	    Circles: Holds X center coordinate.

	    Blits: Holds X coordinate for destination rectangle.

	    Polygon fill: Holds X coordinate of a triangle.



The YDST Register (offset 0x216):
	
	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |Y11|Y10|Y9 |Y8 |Y7 |Y6 |Y5 |Y4 |Y3 |Y2 |Y1 |Y0 |
	 -----------------------------------------------------------------

	Multipurpose register used as shown for the following operations:

	    Vectors: Holds Y stopping coordinate.

	    Circles: Not used

	    Blits: Holds Y coordinate for destination rectangle.

	    Polygon fill: Holds Y coordinate of a triangle.



The XMIN register (offset 0x218):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |X11|X10|X9 |X8 |X7 |X6 |X5 |X4 |X3 |X2 |X1 |X0 |
	 -----------------------------------------------------------------

	The XMIN register contains the x coordinate of the upper left hand
	corner of the pixel clipping region.  Pixel clipping is inclusive,
	i.e. pixels may be drawn on the clip limits.



The YMIN register (offset 0x21c):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |Y11|Y10|Y9 |Y8 |Y7 |Y6 |Y5 |Y4 |Y3 |Y2 |Y1 |Y0 |
	 -----------------------------------------------------------------

	The YMIN register contains the y coordinate of the upper left hand
	corner of the pixel clipping region.  Pixel clipping is inclusive,
	i.e. pixels may be drawn on the clip limits.



The XMAX register (offset 0x21a):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |X11|X10|X9 |X8 |X7 |X6 |X5 |X4 |X3 |X2 |X1 |X0 |
	 -----------------------------------------------------------------

	The XMAX register contains the x coordinate of the lower right hand
	corner of the pixel clipping region.  Pixel clipping is inclusive,
	i.e. pixels may be drawn on the clip limits.



The YMAX register (offset 0x21e):

	 |D15|D14|D13|D12|D11|D10|D9 |D8 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 |
	 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	 | - | - | - | - |Y11|Y10|Y9 |Y8 |Y7 |Y6 |Y5 |Y4 |Y3 |Y2 |Y1 |Y0 |
	 -----------------------------------------------------------------

	The YMAX register contains the y coordinate of the lower right hand
	corner of the pixel clipping region.  Pixel clipping is inclusive,
	i.e. pixels may be drawn on the clip limits.


So that data cannot be changed when it could cause misoperation of RUG, 
registers may be written only under certain conditions.  Any attempt to
write to them when the chip is not ready will have no effect and IMA will
not be asserted.  All readable registers may be read at any time.  The 
following registers may only be changed when RUG is Ready For Data 
(RFD is TRUE):

	XSRC	YSRC	XDST	YDST	XS/XD

All other registers may only be written when RUG is not busy.





			OPERATION SEQUENCES

NOTE: To trigger an operation, add 0x100 to the offset of any register
operation.  For example, if the trigger operation is to be a write to
the YDST register, instead of writing to 0x212, write to 0x312.


VECTOR DRAWING

	Step 1. Set up the COMMAND register
		0x0000 : Solid vectors not drawn (for picking)
		0x0010 : Solid vectors drawn
		0x0040 : Linetype vectors not drawn (for picking)
		0x0050 : Linetype vectors drawn

	Step 2. Load the XSRC register with the starting x coordinate.

	Step 3. Load the YSRC register with the starting y coordinate.

	Step 4. Load the XDST register with the stopping x coordinate.

	Step 5. Load the YDST register with the stopping y coordinate
		and trigger the operation.


CIRCLE DRAWING

	Step 1. Set up the COMMAND register
		0x0020 : Hollow circles not drawn (for picking)
		0x0030 : Hollow circles drawn
		0x0060 : Linetype hollow circles not drawn (for picking)
		0x0070 : Linetype hollow circles drawn
		0x00e0 : Filled circles not drawn (for picking)
		0x00f0 : Filled circles drawn

	Step 2. Load the XS/XD register with x center. 
	
	Step 3. Load the YSRC register with the y center.
	
	Step 4. Load the FY register with the radius and trigger the operation.


BLIT OPERATIONS

	Step 1. Set up the COMMAND register
		0x0090 : Blit mode

	Step 2. Load the FX register with the width of the source region.

	Step 3. Load the FY register with the height of the source region

	Step 4. Load the XSRC register with the upper left hand corner x
		coordinate of the source region.

	Step 5. Load the YSRC register with the upper left hand corner y
		coordinate of the source region.

	Step 6. Load the XDST register with the upper left hand corner x
		coordinate of the destination region.

	Step 7. Load the YDST register with the upper left hand corner y
		coordinate of the destination region and trigger the operation.



PIXEL REPLICATION: RUG provides support for pixel replication by allowing 
		   the duplication of lines in the vertical direction during 
		   blits.  Each line may be duplicated from 1 to 15 times 
		   (magnification 1-16). 

	Step 1. Set up the COMMAND register
		0x0094 : Blit mode with vertical pixel replication.

	Step 2. Load the Expansion Factor and Replication Counter fields of
		the LTP register with the magnification factor as computed
		below:

			magnification factor = 0xf - <duplication count>

 		where the duplication count (0-15) represents the magnifcation
		desired (1-16).  For example, if the desired magnification
		was 2X, magnifcation factor = 0xf - 0x1 = 0xe, so 0x0ee0
		would loaded into LTP.

	Step 3. Load the FX register with the width of the destination region.

	Step 4. Load the FY register with the height of the destination region

	Step 5. Load the XSRC register with the upper left hand corner x
		coordinate of the source region.

	Step 6. Load the YSRC register with the upper left hand corner y
		coordinate of the source region.

	Step 7. Load the XDST register with the upper left hand corner x
		coordinate of the destination region.

	Step 8. Load the YDST register with the upper left hand corner y
		coordinate of the destination region and trigger the operation.



FILL OPERATIONS

	Step 1. Set up the COMMAND register
		0x00c0 : Fill mode, triangles not drawn (for picking)
		0x00d0 : Fill mode, triangles drawn

	Step 2. Load the FX register with the x anchor point.

	Step 3. Load the FY register with the y anchor point.  The anchor
		point is the point in the list of endpoints that has the
		smallest y coordinate.

	Step 4. Load the XSRC register with a x coordinate of the triangle.

	Step 5. Load the YSRC register with a y coordinate of the triangle.

	Step 6. Load the XDST register with the other x coordinate of the
		triangle.

	Step 7. Load the YDST register with the other y coordinate of the 
		triangle and trigger the operation.

	Step 8. Wait for RUG to become not busy, if not done then move to 
	        the next triangle and goto to step 4.


	NOTE: The COMMAND register must be set to fill mode before the 
	      anchor point is loaded and the anchor point must be loaded
	      before loading the other coordinates.


POLYGON DRAWING : The polygon fill algorithm that RUG implements consists
		  of several steps.  The FILL mode in RUG is one of those
		  steps.  Basically each polygon is broken down into triangles,
		  each one consisting of an anchor point and two consecutive
		  vertices, which are drawn using XOR drawing mode in a special
		  non-displayed plane called the scratch plane.  Because
		  of the drawing mode, each piece of the polygon that is 
		  drawn an even number of times will be erased and each piece
		  of the polygon that is drawn an odd number of times will
		  remain.  Because the algorithm must work for triangles that
		  are butted up against each other, the triangle fill does not
		  draw the leftmost pixel of scan lines or the upper most
		  scan line.  To correct this, the finished polygon must be
		  edged.  Finally, the polygon is blitted from the scratch
		  plane to the displayed planes.  The complete algorithm is
		  detailed below.

	Step 1. Scan data to determine bounding box and anchor point.

	Step 2. Clear area in bounding box in scratch plane.

	Step 3. Set drawing mode to XOR and use FILL mode to draw polygon
		in the scratch plane.

	Step 4. Set drawing mode to SOURCE and edge the polygon in the
		scratch plane.

	Step 5. Blit the finished polygon to the displayed planes.



SERIAL INPUT : Vectors and Circles may also be drawn using the serial input
	       port.  To enable the serial mode, bit 1 must be set in the
	       COMMAND register.  After 13 data bits have been clocked into
	       RUG, the operation is triggered.  The next vector or circle
	       may then be loaded into RUG when RFD is true.  Blit and Fill
	       operations will not operate correctly through the serial port.
	       Bit 1 of the COMMAND register must be cleared before using
	       the processor port to trigger an operation.

	Step 1. Set up the COMMAND register
		0x0002 : Solid vectors or hollow circles not drawn (for picking)
		0x0012 : Solid vectors or hollow circles drawn
		0x0041 : Linetype vectors or hollow circles not drawn (for picking)
		0x0051 : Linetype vectors or hollow circles drawn
		0x00e1 : Filled circles not drawn (for picking)
		0x00f1 : Filled circles drawn

	Step 2. Load the FY register with the radius (if in Circle mode).
		Once a radius has been loaded, it may be re-used for
		multiple circles.

	Step 3. Load the data into the serial ports.  Bit 13 (MSB) of XSRC
		will determine if the operation is to be a vector or circle.
		If the mode is for filled circles, this bit must be set.
		After the 13th bit has been clocked in, the operation will
		be triggered.

	Step 4. When RFD goes true again, new data may be clocked in allowing
		pipelined operation.




			REUSING DATA IN REGISTERS

RUG does not change data in registers for the VECTOR, CIRCLE and BLIT
operations.  Once a register has been loaded with a value, that register
need not be changed for new operations.  For example, once the COMMAND
register has been set to CIRCLE mode and the FY register has been loaded
with the radius, many circles of the same radius may be drawn by just changing
the XS/XD and YSRC registers and triggering the operation.

The FILL operation destroys data in the XSRC, YSRC, XDST and YDST registers.
These registers must be rewritten for every triangle.  The anchor point in
the FX and FY registers is not destroyed.




			PICKING

RUG provides support for picking functions through the use of a PICK bit.
This bit is set whenever a VECTOR, CIRCLE or FILL operation results in 
pixels that can be drawn.  It can only be reset by clearing the PICK
bit in the COMMAND register.  A typical application is to load the
clip limits with the picking region, enable clipping and set RUG to 
draw a primitive without enabling output to the frame buffer (bit 4 of
COMMAND).  This allows the chip to run a full speed without disturbing
the contents of the frame buffer.  After each primitive is drawn, or 
after a group of primitives has been drawn, the PICK bit is read
to see if any of the primitives were within the clip limits.



			CLIPPING

Clipping can be enabled to occur on pixel boundries.  Clipping
affects only write cycles so the source of a BLIT operation may be
outside the clip limits.  When enabled, clipping is inclusive,
i.e. pixels will be drawn on the clip limits.  

In order to generate correctly clipped primitives, clipping occurs
after pixel generation.  This means that for objects that are mostly
clipped, RUG will be busy 1 or 2 clock cycles for each pixel that
is clipped but not displayed.

